Patents Assigned to Sun Microsystems
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Publication number: 20040001505Abstract: A circuit for a plus one operation includes a means for incrementing a first bit set of a binary number and a means for detecting a zero in any bit set less significant than the first bit set, the means for detecting being coupled to the means for incrementing. The means for incrementing operates in a first mode when the means for detecting detects a zero in any bit set less significant than the first bit set and operates in a second mode when the means for detecting does not detect a zero in any bit set less significant than the first bit set.Type: ApplicationFiled: June 27, 2002Publication date: January 1, 2004Applicant: Sun Microsystems, Inc.Inventors: Ken L. Motoyama, Sudhendra V. Parampalli
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Publication number: 20040002992Abstract: A multiprocessor computer system is configured to selectively transmit address transactions through an address network using either a broadcast mode or a point-to-point mode transparent to the active devices that initiate the transactions. Depending on the mode of transmission selected, either a directory-based coherency protocol or a broadcast snooping coherency protocol is implemented to maintain coherency within the system. A computing node is formed by a group of clients which share a common address and data network. The address network is configured to determine whether a particular transaction is to be conveyed in broadcast mode or point-to-point mode. In one embodiment, the address network includes a mode table with entries which are configurable to indicate transmission modes corresponding to different regions of the address space within the node.Type: ApplicationFiled: June 23, 2003Publication date: January 1, 2004Applicant: Sun Microsystems, Inc.Inventors: Robert E. Cypher, Ashok Singhal
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Publication number: 20040003365Abstract: A method performs an operation on physical design data stored as data objects in a database. Each data object represents a design figure of an integrated circuit (IC) design laid-out on an IC design area. The method includes (a) dividing the IC design area into a second plurality of sub-areas, (b) assigning an area property to each of the data objects, the area property indicating the sub-areas on which at least part of the corresponding design figure is to be located, (c) selecting a first data object, and (d) conducting an operation involving the first data object and a second data object involving selecting the second data object from a subset of data objects having an area property indicating a sub-area indicated by an area property of the first data object, and performing the operation on the first data object and the second data object.Type: ApplicationFiled: June 27, 2002Publication date: January 1, 2004Applicant: Sun Microsystems, Inc. a Delaware CorporationInventor: Alexander I. Korobkov
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Publication number: 20040002955Abstract: A registry service is described which uses a partitioned publisher assertion recording and accessing scheme. A publisher assertion regarding a relationship between entities (e.g., business or other types of entities) is encoded within a directory information tree in a memory. The publisher assertion includes publisher assertion part nodes corresponding to entity nodes in the directory information tree. The publisher assertion is complete if all publisher assertion parts corresponding to entities in the relationship are present in the directory information tree. The service may include a network including directory servers and registry servers. The publisher assertions are manipulated by authorized publishers and accessed by users using a variety of techniques, the operations of which are performed by such parties and/or are encoded upon computer-readable media.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Applicant: Sun Microsystems, Inc.Inventors: David Gregory Gadbois, Mark Wahl
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Publication number: 20040002847Abstract: A present invention discloses an automated method to generate an eye-plot for signals produced by a simulation or captured hardware results. The automated approach is customizable in that the designer may specify input parameters to customize the analysis to fit the needs of the user. The eye-plot is then generated. The eye-plot may be output on the printer, displayed on the video display or even stored in secondary storage for subsequent review and use.Type: ApplicationFiled: June 26, 2002Publication date: January 1, 2004Applicant: Sun Microsystems, Inc.Inventors: Robert D. Cole, William B. Gist
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Publication number: 20040002960Abstract: An information processing system includes a runtime versioning facility which allows for managing its configuration so that modifications made during runtime are propagated and take affect without restarting the system or a portion thereof. This allows the potential for 100% uptime while upgrading such systems. This also provides a system capability to process multiple configuration versions, and to be able to process such versions even while such versions are changing during operation of the information processing systems. For example, a system such as a registry server capable of transactional configuration changes is provided which manages its configuration so that modifications made during runtime are propagated and take affect without restarting the server.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Applicant: Sun Microsystems, Inc.Inventors: William Trey Drake, Kent Arthur Spaulding, David Gregory Gadbois
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Publication number: 20040003208Abstract: A processor includes a set of registers, each individually addressable using a corresponding register identification, and plural virtual registers, each individually addressable using a corresponding virtual register identification. The processor transfers values between the set of registers and the plural virtual registers under control of a transfer operation. The processor can include a virtual register cache configured to store multiple sets of virtual register values, such that each of the multiple sets of virtual register values corresponds to a different context. Each of the plural virtual registers can include a valid bit that is reset on a context switch and set when a value is loaded from the virtual register cache. The processor can include a virtual register translation look-aside buffer for tracking the location of each set of virtual register values associated with each context.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Applicant: Sun Microsystems, Inc.Inventor: Peter C. Damron
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Publication number: 20040003019Abstract: Managing a task in a system management controller may be accomplished by storing information regarding the task in a process control buffer. A state of the task stored in the process control buffer may be examined to determine if it is active. If so, then a task counter contained in the process control buffer can be examined to determine if the task should be run immediately, or at a later time. If it is immediately, the task is immediately executed. If not, then timer fields may be examined to determine precisely when the task should be executed. The task counter may also indicate the number of times the task should be executed, or if it should be executed indefinitely. Thus, the method may be restarted with a new process control buffer if the timer fields are not less than or equal to a current time.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Applicant: Sun Microsystems, Inc., a Delaware CorporationInventors: Gunawan Ali-Santosa, Rahmat Mortazavi
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Publication number: 20040003211Abstract: In a set of registers, each individually addressable by register operations using a corresponding register identification, at least one register of the set of registers is an extended register having multiple storage locations. Values stored in the multiple storage locations are accessed, for example, according to the order in which they have been stored. Less than all of the multiple storage locations are accessible by a register operation at a given time. Older versions of software that do not recognize extended registers identify the extended register as having only one storage location. An extended register can be, for example, a stack register, a queue register, or a mixed register and values stored in the multiple storage locations are read and stored according to the characteristics of the register.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Applicant: Sun Microsystems, Inc.Inventor: Peter C. Damron
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Publication number: 20040003148Abstract: A buffer block allocation table as well as a buffer allocation table may be provided to handle a buffer request in a system management controller. When a buffer request is received, the buffer block allocation table may be scanned entry-by-entry to find an available buffer block. once one its located, it is marked as taken. Then, the corresponding buffer block in the buffer allocation table is scanned entry-by-entry looking for one that is available. If one is found, it is used for the buffer request. If one cannot be found, the system may return to the buffer block allocation table and continue with the next entry. This process may repeat until an available buffer is found.Type: ApplicationFiled: November 14, 2002Publication date: January 1, 2004Applicant: Sun Microsystems, Inc., a Delaware CorporationInventors: Gunawan Ali-Santosa, Rajeev Bharol
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Patent number: 6671196Abstract: A CPU includes a register file including a plurality of architectural registers for storing data loaded from a primary memory for execution by the CPU. A stack cache memory coupled to the register file includes a plurality of cache lines, each of which corresponds to one of the architectural registers and implements a first-in, last-out queue for data spilled from the corresponding architectural register. Data spilled from the register file into the stack cache memory is maintained in the stack cache until subsequently restored to the register file without accessing primary memory. The stack cache memory does not participate in cache writeback operations to primary memory.Type: GrantFiled: February 28, 2002Date of Patent: December 30, 2003Assignee: Sun Microsystems, Inc.Inventor: Jan Civlin
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Patent number: 6671796Abstract: A method and apparatus are provided for performing efficient conversion operations between floating point and fixed point values on a general purpose processor. This is achieved by providing an instruction for converting a fixed point value fx into a floating point value fl in a general purpose processor. Accordingly, the invention advantageously provides a general purpose processor with the ability to execute conversion operation between fixed-point and floating-point values with a single instruction compared with prior art general purpose processors that require multiple instructions to perform the same function. Thus, the general purpose processor of the present invention allows for more efficient and faster conversion operations between fixed-point and floating-point values.Type: GrantFiled: February 25, 2000Date of Patent: December 30, 2003Assignee: Sun Microsystems, Inc.Inventors: Subramania Sudharsanan, Jeffrey Meng Wah Chan, Michael F. Deering, Marc Tremblay, Scott R. Nelson
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Patent number: 6671690Abstract: Methods and apparatus for deleting a member in a circular singly linked list are described. Just prior to the current pointer register being updated, its contents are copied to the previous pointer register. When the consumer needs to delete a member from the list, the previous member location is known because it is saved in the previous pointer register. In this way, deletions done at the time of scanning involve only a single SRAM write access since the contents of the current pointer register is copied into the member referenced by the previous pointer register.Type: GrantFiled: April 10, 2001Date of Patent: December 30, 2003Assignee: Sun Microsystems, Inc.Inventors: Thomas Peter Webber, Hugh Kurth
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Patent number: 6671841Abstract: A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuit's core logic primary storage elements. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the primary storage elements is then scanned out via the shadow scan path without altering the primary storage elements using special commands issued from a JTAG controller. This shadow scan system allows a circuit to remain operational while a snapshot of the core logic information is scanned out.Type: GrantFiled: October 5, 2000Date of Patent: December 30, 2003Assignee: Sun Microsystems, Inc.Inventor: Farideh Golshan
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Patent number: 6671863Abstract: A method for optimizing loop bandwidth in a phase locked loop is provided. A representative power supply waveform having noise is input into a simulation of the phase locked loop; an estimate of jitter is determined; and the loop bandwidth of the phase looked loop is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing loop bandwidth in a phase locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize loop bandwidth in a phase locked loop is provided.Type: GrantFiled: February 14, 2002Date of Patent: December 30, 2003Assignee: Sun Microsystems, Inc.Inventors: Claude Gauthier, Brian Amick, Dean Liu, Pradeep Trivedi
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Patent number: 6670959Abstract: A graphics system that may be shared between multiple display channels includes a frame buffer, an arbiter, and two pixel output buffers. The arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer is divided into a first and a second portion. The arbiter alternates display channel requests for data between the first and second portions of the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the output buffers. The arbiter selects which request to forward to the frame buffer based on a relative state of neediness of each of the requesting display channels.Type: GrantFiled: May 18, 2001Date of Patent: December 30, 2003Assignee: Sun Microsystems, Inc.Inventors: Michael A. Wasserman, Michael G. Lavelle, David C. Kehlet, Glenn Gracon
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Publication number: 20030236930Abstract: Provided are a method, system, and program for managing access to a device. An I/O request directed toward the device is received and a determination is made of a device object for the device associated with at least one path object. A determination is made of a queue object associated with the device object, wherein the queue object corresponds to one queue. A determination is made of a queue status from the determined queue object and the I/O request is transmitted on a path indicated in the path object that is associated with the determined device object if the queue status is set to a state indicating to transmit I/O requests.Type: ApplicationFiled: May 28, 2002Publication date: December 25, 2003Applicant: Sun Microsystems, Inc.Inventor: Stephen D. Paul
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Publication number: 20030237060Abstract: The present invention provides a solution for converting a boundary scan description language (BSDL) file to a hardware verification language (HVL) test program file. The BSDL file is scanned for header information and the header information is stored in a header object. The BSDL file is then scanned for pin information, the pin information corresponding to at least one pin in the BSDL file having a pin location, and stored in a pin object. At least one variable for the HVL test program file is created and bound to one of the pin locations resulting in a binding relationship for each variable. The binding relationships are then stored in a bind object. The present invention is designed to overcome the disadvantages of the prior art.Type: ApplicationFiled: June 20, 2002Publication date: December 25, 2003Applicant: Sun Microsystems, Inc., a Delaware CorporationInventors: Keshava I. Satish, Neil Korpusik
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Publication number: 20030236998Abstract: A method includes providing at least one field replaceable unit in a computer system. The field replaceable unit has a memory device configured to store field replaceable unit data. An authentication check is performed on the field replaceable unit data. The field replaceable unit is identified as being unqualified responsive to a failure of the authentication check. A computer system includes at least one field replaceable unit and a system controller. The field replaceable unit has a memory device configured to store field replaceable unit data. The system controller is configured to perform an authentication check on the field replaceable unit data, and identify the field replaceable unit as being unqualified responsive to a failure of the authentication check.Type: ApplicationFiled: April 14, 2003Publication date: December 25, 2003Applicant: Sun Microsystems, Inc.Inventors: Raymond J. Gilstrap, Emrys Williams, Robert Abramovitz
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Patent number: D484509Type: GrantFiled: May 20, 2002Date of Patent: December 30, 2003Assignee: Sun Microsystems, Inc.Inventors: Christopher H. Frank, Adam Richardson