Abstract: An apparatus for private personal identification number (PIN) management comprises a memory and a PIN comparator in communication with the memory. The PIN comparator is configured to ascertain a first delay period of a preceding PIN. The first delay period is greater than zero if the preceding PIN does not match a validated PIN and the first delay period equals zero if the preceding PIN matches the validated PIN. The PIN comparator is further configured to receive a current PIN after at least the first delay period and delay for a second delay period if the current PIN does not match the validated PIN. The second delay period is greater than the first delay period.

Abstract: The electronic device with a system for enhancing the cooling of components located therein is provided. The device includes a housing with a fan positioned adjacent the housing and adapted for producing airflow within the housing. The printed circuit board is mounted within the housing, and a heat-producing device is mounted on the printed circuit board. The heatsink is coupled to the heat-producing device, and a shroud is mounted on the printed circuit board and extends up to the heatsink so as to improve airflow in the region adjacent the heatsink.

Abstract: A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuit's core logic primary storage elements. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the primary storage elements is then scanned out via the shadow scan path without altering the primary storage elements using special commands issued from a JTAG controller. This shadow scan system allows a circuit to remain operational while a snapshot of the core logic information is scanned out.

Abstract: Clocked charge recycling differential logic circuits are activated by a delayed clock. According to the invention, when clocked charge recycling differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked charge recycling differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked charge recycling differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked charge recycling differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked charge recycling differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A computer network has a subnetwork of computers including a server, a first authentication server, a firewall, and network interconnect. This subnetwork is connected through encrypted protocol handlers and over a potentially insecure channel to a second authentication server. Some authentication requests, especially for users not authenticated in the first authentication server's database and determined by the first authentication server to be authenticatable by the second authentication server, are passed from the server of the subnetwork through the encrypted protocol handlers and over the potentially insecure channel to the second authentication server.

Abstract: An enclosure includes a base having an interior portion defined by a first side panel and a second side panel and a frame joined to the first side panel and the second side panel such that the frame extends across the interior portion the base. A computer system includes a motherboard having a central processing unit, a power supply capable of supplying power to the motherboard, and an enclosure capable of housing the motherboard and the power supply. The enclosure includes a base having an interior portion defined by a first side panel and a second side panel and a frame joined to the first side panel and the second side panel such that the frame extends across the interior portion of the base.

Abstract: A method and apparatus to determine skew of an on-chip signal without physical probing of the on-chip signal on the chip is provided. The method and apparatus use an externally generated reference signal that is distributed to one or more on-chip samplers that input the on-chip signal. Then, by modulating the externally generated reference signal, transitions of the on-chip signal can be detected at the one or more on-chip samplers so that the skew of the on-chip signal can be determined.

Abstract: A memory array management unit suitable for use in a computer graphics system is described. The unit is especially designed to facilitate the storage of tiles of graphics data. Alignment detection between the tiles and memory block boundaries is provided for, with misalignments resulting in the automatic decimation to produce sub-tiles and generation of multiple memory write sequences.

Abstract: A system and method are provided for ensuring delivery of a communication from one computer system or node to another. A first node includes an object handler, such as an ORB (Object Request Broker), that receives object references from higher-level services operating on the first node, wherein the referenced object resides on a second node. The first node's object handler generates a message to an object handler on the second node and attempts to send the message to the second node through a transport module. The message is assigned a unique identifier, such as a sequence number. If the first object handler receives an uncertain status concerning the message (e.g., other than a certain success or failure), it issues a query to the second node to determine if the message was received. If the query is received by the second object handler before the message itself is received, the message is considered lost or rescinded by the first node.

Abstract: A method and apparatus for packet-switched flow control of transaction requests in uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller a piori know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate.

Abstract: A rack mountable system unit includes a housing having first and second sides. First and second elongate plastics slides are secured to respective sides of the system unit. Each plastic slide is dimensioned to slide within a rack mountable rail and is tapered at one end thereof to facilitate insertion into the rail. The tapered end of the slides facilitates insertion into the rails and the use of plastics facilitates sliding. The maximum height of the slide is dimensioned to slide within the rack mountable rail. To further facilitate the sliding of the system unit along the racking, the sides include narrower portions alternating with portions dimensioned to slide within the rack mountable rail. The slides each have a flange and a releasable fixing at a front end thereof for securing the system unit to rack mountable rails.

Abstract: One embodiment of the present invention provides a system that selects instructions to be executed in a computer system that supports out-of-order execution of program instructions. The system receives dependency information for a first instruction. This dependency information identifies preceding instructions in the execution stream of a program that need to complete before the first instruction can be executed. The system divides this dependency information into a recent set and a less recent set. The recent set includes dependency information for a block of instructions immediately preceding the first instruction that need to complete before the first instruction can be executed. The less recent set includes dependency information for instructions not in the block of instructions immediately preceding the first instruction that need to complete before the first instruction can be executed.

Abstract: A component cage for detachable mounting an ancillary component such as a hard disc drive in a housing for an electronic circuit is described. The cage has internal step surfaces to engage support runners of the component. The formation of elongated slots in the cage to accommodate support runners is avoided, improving the electromagnetic shielding ability of the cage.

Abstract: Disclosed is a method and circuit for variably controlling a delay line for read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input strobe signal. The variably controlled delay circuit also receives a multibit control code. The variably controlled delay circuit transmits the input strobe signal after a time delay, wherein the time delay varies according to the multibit control code. The FIFO is coupled to the variably controlled delay circuit and receives the time delayed strobe signal therefrom. The FIFO is receives an input data bit signal. The FIFO stores the input data bit signal in response to receiving the time delayed strobe signal.

Abstract: A handle for ejecting a fan tray from an electronics enclosure comprises an elongated lever arm and a pair of opposing spring tabs extending from the lever arm disposed at an end of the lever arm. In an embodiment of the invention, the handle further includes a first bushing protruding from one of the opposing spring tabs and a second bushing protruding from a second one of the opposing spring tabs. The first bushing and the second bushing define a pivot axis substantially perpendicular to a long axis of the elongated lever arm, and are configured to snap into opposing retention features of the fan tray. The elongated lever arm is thereby attached to the fan tray and pivotable between a closed position folded against an end of the fan tray, and an open position extending from the fan tray. In another embodiment, the handle further includes a bump edge protruding from the end of the elongated lever arm in a direction opposite to the pair of opposing spring tabs.

Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: A method for characterizing a timing value of a timing-sensitive digital logic circuit includes (a) setting a set of input signal parameters such that the transition edge of an input signal is placed a selected time interval from an active edge of a clock signal, (b) conducting a circuit simulation, (c) observing an output signal and determining validity thereof, (d) shifting the transition edge by a window having a given time width, (e) simulating the circuit so as to determine the validity of the output signal, (f) iterating the shifting and the simulating by doubling the time width of the window for each iteration unless the doubled time width exceeds half the clock cycle and until the validity of the output signal changes, and (g) defining a solution window between the transition edge yielding the last valid output signal and the transition edge yielding the last invalid output signal.

Abstract: Disclosed is a high voltage decoupling capacitor-biasing circuit with no dc current. In one embodiment, the circuit includes a power supply node, a ground node, a common node, a first p-channel FET, a first n-channel FET, and a common node biasing circuit. The first p-channel FET includes a source, gate, and drain, wherein the source and drain of the first p-channel FET are coupled to the power supply node, and wherein the gate of the first p-channel FET is coupled to the common node The first n-channel FET includes a source, gate, and drain, wherein the source and drain of the first n-channel FET are coupled to the ground node, and wherein the gate of the first n-channel FET is coupled to the common node. The common node biasing circuit is coupled between the power supply and ground nodes. The common node biasing circuit is configured to maintain the common node at a predetermined voltage above ground by charging up or charging down the common node.

Abstract: An invention is provided for incorporating web services into JSP tag libraries for use in JSP pages. As a result, web page authors can develop JSP pages, which utilize web services from WSDL enabled servers, without an in-depth knowledge of WSDL. In general, a web services based document is received, which defines a set of web service operations. Each web service operation is translated into a custom action, and the custom actions are grouped into a tag library. Generally, the web services based document can be a WSDL document, and the custom actions can be JSP custom actions. Also, the tag library can be a JSP custom tag library. Particular custom actions from the custom actions that are grouped in the JSP custom tag library can be incorporated in a JSP page. Once the JSP page is created, content for the JSP page can be obtained from a web service using the JSP custom tag library. The JSP page can then generate a document based on the content.

Abstract: Provided are a method, system, and program for managing access to at least one device coupled to a computer system. A set of operating specific functions perform operating system related operations related to managing access to the at least one device. A set of device specific functions performs operations that interact with the device. The operating system specific functions and device specific functions are loaded into memory. Pointers to the operating system specific functions and device specific functions in memory are added to at least one function pointer list accessible to a device specific module and operating system module executing in the computer system. The device specific module and the operating system specific module access the pointers in the function pointer list to call the operating system specific functions and device specific functions.