Abstract: A test system for testing communications over a bus connecting electronic devices, e.g., components of a computer system is preferably embedded in the devices themselves rather than in apparatus external to them, and is responsive to digital control signals, e.g., conforming to JTAG, for scanning test data into and out of the devices. The test system has a stress injection module for injecting a set of stimulus patterns on the bus; an error identification module for identifying an error resulting from the set of stimulus patterns; a bus tuning module for adjusting one or more bus operating and signaling parameters so that testing can be performed at one or more of a number of different sets of operating and signaling parameters; a programmable control module for controlling the bus tuning module; and a presentation module for presenting a plurality of results of the testing.

Abstract: A system for executing a software application comprising a plurality of hardware independent bytecodes is provided comprising a computing system that generates bytecodes, a virtual machine, remote to the computing system, that receives a plurality of bytecodes from said computing system, and executes said plurality of bytecodes, a system for testing said bytecodes against a set of predetermined criteria in which the testing is securely distributed between said virtual machine and said computing system so that the bytecode verification completed by the computing system is authenticated by the virtual machine prior to the execution of the bytecodes by said virtual machine. A method for distributed bytecode verification is also provided.

Abstract: One embodiment of the present invention provides a system that performs, content screening on a message that is protected by end-to-end encryption. The system operates by receiving an encrypted message at a firewall from a source outside of the firewall, the encrypted message having been formed by encrypting the message with a message key. In order to restore the message, the system procures the message key and decrypts the encrypted message with the message key. Next, the system screens the message within the firewall to determine whether the message satisfies a screening criterion. If so, the system allows a destination within the firewall to process the message. In one embodiment of the present invention, procuring the message key includes allowing the source and the destination to negotiate the message key, which is then sent to the firewall.

Abstract: In accordance with methods and systems consistent with the present invention, an improved processor performance instrumentation system is provided that allows a software tester to measure more performance indicators than there are hardware counters during a single execution of a tested program. The improved processor performance instrumentation system accomplishes this by “multiplexing” performance indicators while executing the tested program. In effect, methods and systems consistent with the present invention extend the abilities of the limited number of hardware counters to allow them to measure a number of performance indicators otherwise not allowed during one execution of the tested program.

Abstract: A system and method of measuring extinction ratio and deterministic jitter of an optical transceiver. The measurement system includes a computing node and an oscilloscope coupled to the computing node. The oscilloscope is also coupled to the optical transceiver. The oscilloscope is configured to capture a waveform of a predetermined data pattern transmitted by the optical transceiver. The oscilloscope is configured to capture the waveform in a non-persistent mode using waveform averaging. The oscilloscope is also configured to perform measurements on the waveform. The computing node is configured to program the oscilloscope to perform the measurements on the waveform. The computing node is also configured to calculate an extinction ratio and to compare the extinction ratio to an acceptable standard. The computing node is also configured to calculate a deterministic jitter value of the optical transceiver in response to the extinction ratio being within the acceptable standard.

Abstract: A method and apparatus for modeling the specular reflection of light from an object is disclosed. In accordance with one embodiment of the method, a portion of the object is modeled by one or more surfaces each having at least one vertex and an edge point corresponding to an edge. A sine value associated with a highlight angle is determined at each vertex and edge point, and a control value is determined at each vertex and edge point using the sine values. A specular input component at each point on the surface is determined using the control values. The specular input component is utilized to determine the specular light component at that particular point. Embodiments of apparatus implementing the method are also disclosed.

Abstract: A browser-independent and automatic apparatus and method for receiving, installing, and launching applications from a browser is described. According to one embodiment, a helper application is registered with a browser for a specified file type. When the browser encounters a link to a metafile of the specified file type, the file is downloaded to the requesting system and the helper application is invoked to process the downloaded file. In the context of a Java™ implementation, the downloaded metafile comprises a short launch file specification for a Java™ application, and specifies a classpath as a set of Universal Resource Identifiers (“URIs”), a Java™ Runtime Environment (“JRE”) version, security considerations, and other relevant information concerning the Java™ application to be executed.

Abstract: A computer system has a program module verifier and at least first and second program modules. Each program module includes a digital signature and an executable procedure. The first program module furthermore includes a procedure call to the second procedure module, a procedure call to the program module verifier that is logically positioned in the first program module so as to be executed prior to execution of the procedure call to the second program module, and instructions preventing execution of the procedure call to the second program module when the procedure call to the program module verifier results in a verification denial being returned by the program module verifier.

Abstract: Hold time methods, systems, and computer program products are implemented to ensure that storage elements in a circuit have sufficient hold times without detrimentally affecting cycle times for other paths in the circuit. Electric circuits are designed by determining which storage elements have hold-time deficiencies, and by inserting an appropriate time delay element in a selected path preceding the storage element, or at a source or destination storage element, without exceeding a predetermined cycle time in a second path that overlaps the first path, for at least one storage element in an electrical circuit. The invention simulates insertion of the time delay element before or after a logic element that precedes a storage element that has a hold-time deficiency.

Abstract: A new interface and methods allow a new versatility both in both managing a database, and in presenting hierarchical database information in a more useful way. User marks are used to determine the visibility of the elements at the various hierarchical levels in a hierarchical directory structure of a database. Hence, the user marks are user hierarchical visibility marks. The user hierarchical visibility marks are automatically propagated to other elements in the structure according to a filter selected by the user, for example.

Abstract: A system including a rendering engine, a sample buffer and a filtering unit. The rendering engine is configured to render samples in response to received graphics data. The sample buffer is configured to receive and store the samples. The filtering unit is configured to read and filter the samples stored in the sample buffer to generate pixel values. The filtering unit includes a counter controller, a set of positive counters and a set of negative counter. The counter controller is configured to accumulate a histogram of exponent values of the pixel values in the positive counters and negative counters. The positive counters maintain count values for exponents of positively signed pixel values and the negative counters maintain count values for exponents of negatively signed pixel values.

Abstract: A system and method for discovering nodes in an M×N torus interconnection fabric of nodes is provided. The method comprises probing an M×N torus interconnection fabric, wherein M and N are integer values and said interconnection fabric includes a first plurality of nodes forming an x-axis and a second plurality of nodes forming a y-axis; and identifying a location of a first node relative to the x and y axes. The computer system comprises an M×N array of nodes, wherein M and N are integer values; and a plurality of interconnects connecting the M×N array. A first plurality of nodes in the M×N array form an x-axis in the M×N array, a second plurality of nodes in the M×N array form a y-axis in the M×N array, and a first node in the M×N array is configured to probe the M×N array to identify a location of the first node relative to the x-axis and the y-axis.

Abstract: An editor or software engineering tool may be configured to render whitespace between adjacent tokens, wherein the amount of whitespace between any two adjacent tokens is determined according to language-specific style rules and scaled in accordance with display considerations. In some realizations, the operative scaling is selected or defined by a user according to the user's visual preferences. In some realizations, the operative scaling relates to requirements or constraints of an automated layout mechanism. For example, a particular scaling may be calculated to adjust line length in conformance with a desired margin alignment or to optimize layout when long lines are automatically wrapped (or folded) in some automatic way.

Abstract: The present invention involves a system and method for performing motion estimation. For each candidate motion vector, encoding distortion is determined between a macroblock and a reconstructed macroblock by determining discrete cosine transform cofficients of the macroblock and quantizing the discrete cosine transform coefficients. An estimate unit determines the length of the bit stream required to encode the quantized discrete cosine transform coefficients along with the mode information bits including mode and motion vector information. The reconstructed macroblock is determined based on the quantized discrete cosine transform coefficients. A bit-rate term based on the length of the bit-rate stream is determined and included in the encoding distortion. The candidate motion vector which minimizes the encoding distortion of the macroblock is chosen to be the motion vector for the macroblock.

Abstract: The invention noninvasively provides information relating to memory space allocation. Memory space allocation information is maintained in a location that is known or identifiable outside of the process for which the memory space has, been allocated. A memory space allocator maintains the information in a descriptor block. The descriptor block is updated with every allocation or deallocation of memory space. In the preferred embodiment of the invention, the descriptor block exists on a page of memory having a size equal to the native page size of the machine on which it is, operating. The memory allocator allocates memory space in units referred to as buckets that exist within a memory block. The descriptor block contains an identifier that identifies the memory space allocation information stored in that descriptor block as being controlled by a particular memory space allocator. The descriptor block also contains information that indicates how many pages are used and how many pages are free.

Abstract: The present invention provides a method and apparatus for executing a boundary check instruction that provides accelerated bound checking. The instruction can be used to determine whether an array address represents a null pointer, and whether an array index is less than zero or greater than the size of the array. Three extensions of a boundary check instruction are provided, with each performing a different combination of three boundary check comparisons. One comparison compares a first operand, which may contain the base address of an array, to zero. Another comparison evaluates the value of a second operand, which may contain an index offset, to determine if it is less than zero. The other comparison evaluates whether the value of the second operand is greater than or equal to a third operand. The third operand may indicate the size of an array. A trap is generated if any of the comparisons evaluates to true.

Abstract: A computer system includes a chassis with a single motherboard supporting at least one processor module. A power sub-system receives three power supply units and distributes power within the computer system. Each of the three power supplies has a power rating such that two of the three power supplies are sufficient to power the computer system. The combination of such a single-motherboard-based design with a redundant three-power supply sub-system provides reliability of operation in a cost-effective manner. The power sub-system includes a power distribution board with power distribution logic operable to distribute power from the power supply units for powering the processor module. The power distribution logic is operable to interrupt power for powering the processor module when two of the power supply units fail or are not present. An alarm sub-system is provided for reporting power supply faults.

Abstract: An on-chip DC voltage generator providing a marginable reference voltage signal is described. The present invention is a CMOS-based integrated circuit that generates a marginable reference voltage level. The present invention provides a process insensitive reference voltage signal and may be configured so as to generate a ground-bounce-noise free signal.

Abstract: A computer system housing with a curved bezel that forms one or more sideways gap between a side of the computer housing chassis and the bezel attached to that side. Typically, the curved bezel is attached to the front of the chassis with each sideways gap extending perpendicularly from the front of the chassis to a predetermined width and stretching to predetermined length along the front of the chassis. The sideways gaps facilitate increased air inlet from the sides and allow efficient cooling of various system components that are mounted on the chassis and housed within the housing. One or more cooling fans may be mounted at different locations within the housing to optimize air circulation and, hence, cooling within the housing. The chassis may be partitioned into two separate sub-chassis for proper positioning of the cooling fans as well as to accommodate changes in computer system configurations with minimized retooling of the chassis.

Abstract: A processor performs precise trap handling for out-of-order and speculative load instructions. It keeps track of the age of load instructions in a shared scheme that includes a load buffer and a load annex. All precise exceptions are detected in a T phase of a load pipeline. Data and control information concerning load operations that hit in the data cache are staged in a load annex during the A1, A2, A3, and T pipeline stages until all exceptions in the same or earlier instruction packet are detected. Data and control information from all other load instructions is staged in the load annex after the load data is retrieved. Before the load data is retrieved, the load instruction is kept in a load buffer. If an exception occurs, any load in the same instruction packet as the instruction causing the exception is canceled. Any load instructions that are “younger” than the instruction that caused the exception are also canceled.