Abstract: Conventional virus detection software monitors incoming arrivals of network traffic. Retroactive analysis and/or monitoring of previously accepted traffic is not included in the scope of protection. A retroactive virus detection and propagation history tracking mechanism provides identification of successive recipients of a newly discovered virus which may have eluded detection during the lag time prior to effecting the detection of a new virus. A propagation history maintains a set of recipients receiving a potentially harmful transmission. Upon detection of a particular transmission or portion thereof as being a virus, the propagation history contains a set of infected recipients, which the tracking mechanism notifies so as to perform remedial action and contain the virus to the known set of infected recipients. In this manner, configurations of the invention maintain a set of successive recipients of a virus, and retroactively track and contain the newly propagated virus once detected.

Abstract: A method of converting between a uniform resource locator and a dynamically compressed uniform resource locator involving parsing the components of the uniform resource locator, generating a token that uniquely identifies the combination of a path and a static query string parameter of the uniform resource locator, caching the token, the path, and the static query string parameter, and appending a dynamic query string parameter of the uniform resource locator to the token to form a compressed uniform resource locator.

Abstract: A method for monitoring a plurality of objects, involving configuring a sensor for a first object of the plurality of objects, wherein the sensor monitors an environment of the first object, attaching the sensor to the first object, associating each of the plurality of objects together using a pre-defined stimulus to obtain an associated set of objects, and communicating a notification message when a change in activity of the environment of the first object is detected by the sensor.

Abstract: A method and apparatus for managing data is described which includes determining the current state of a storage tier of a plurality of storage tiers within a storage system. Further, a prediction is made, using a prediction architecture comprising at least one predetermined variable, of the utilities of future expected states for at least two of a plurality of storage tiers involved with a data operation, wherein a future expected state of a corresponding storage tier is based on conditions expected to occur following the completion of the data operation. Finally, the data operation is performed if the predicted utility of the future expected state associated with the at least two of a plurality of storage tiers is more beneficial than the utility of the current state.

Abstract: A remembered set for a memory heap region in a garbage-collected computer system is modified to classify reference locations stored therein by the heap region from which the references originate so that the number of references originating from a given region can be easily determined. If the number of remembered set entries for references from a second region to a first region reaches a predetermined threshold, the second region is constrained so that it will be collected at the same time as, or before, the first region. Then, all entries in the remembered set associated with the first region for references from the second region to the first region can be deleted, and no such entries need be entered in the future thereby reducing the size of that remembered set and the time required to scan it.

Abstract: A method and apparatus for determining predicted failure rates for computational resources provided by a system comprising multiple components. The method comprises storing failure rate information about individual components and determining a current configuration of components within the system. The method further comprises identifying from the current configuration dependencies between components within the system. The stored failure rate information and the identified current configuration dependencies can then be used to generate predicted failure rates for the computational resources in the current configuration of the system.

Abstract: A garbage collector for reclaiming computer-memory space occupied by unreachable data objects operates incrementally in accordance with the train algorithm. Although most objects share car sections with other objects, objects found to be referred to by a large number of references are placed in their own individual car sections so that the “popular” object's train membership can be changed without relocating the object and thus requiring the numerous references to it to be updated. The collector keeps track of different object classes to have instances that are popular. If a class exhibits a strong tendency to have popular instances, the collector initially places instances of that class into respective single-object cars even if those objects have not yet been identified as popular.

Abstract: One embodiment of the present invention provides a system for using register readiness to facilitate value prediction. The system starts by loading a previously computed result for a function to a destination register for the function from a lookup table. The system then checks the destination register for the function by using a Branch-Register-Not-Ready (BRNR) instruction to check the readiness of the destination register. If the destination register is ready, the system uses the previously computed result in the destination register as the result of the function. Loading the value from the lookup table in this way avoids unnecessarily calculating the result of the function when that result has previously been computed.

Abstract: A method and apparatus performs computer application level testing of an instruction cache in multi-processor or multi-core systems. Instruction cache cannot be written to and read from directly. Thus, one microprocessor core is utilized to perform application level testing of an instruction cache of another microprocessor core. The method and apparatus uses two software threads: a controller thread and a target thread. The target thread uses a portion of the instruction cache as a scratch pad for synchronization with the controller thread. The controller thread controls the sequence of operations to perform a March test on the target instruction cache.

Abstract: A system that facilitates optical multiplexing and demultiplexing. The system includes an optical transmitter which is structured in the following way. A wavelength-splitting mechanism is coupled to the optical transmitter, which separates the wavelengths of light onto an array of input-optical-waveguide busses within the optical transmitter. An array of ring modulators within the optical transmitter is coupled to each optical-waveguide bus, wherein the input-end of a given ring modulator is coupled to a corresponding input-optical-waveguide bus. Output-optical-waveguide busses within the optical transmitter are coupled to the array of ring modulators, wherein the output-end of each ring modulator is coupled to a corresponding output-optical-waveguide bus. When a modulation signal is applied to a given ring modulator within the array of ring modulators, a specific wavelength of light is directed to the corresponding output-optical-waveguide bus.

Abstract: An improved approach to cache management is disclosed which may be implemented to provide fine-grained control over individual caches or subsets of a multi-level cache hierarchy. By selectively operating on shared and unshared caches during power management processing, more efficient system operation can be achieved. In one example, a microprocessor is adapted to interface with multiple caches configured in multiple cache levels. The microprocessor includes multiple processors associated with the caches. At least one of the processors is adapted to execute an instruction configured to identify a subset of the caches. The microprocessor also includes a control circuit adapted to perform an operation on the subset of the caches in response to an execution of the instruction by the at least one of the processors.

Abstract: An array-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the array-based algorithm allows uninterrupted concurrent access to both ends of the deque, while returning appropriate exceptions in the boundary cases when the deque is empty or full. An interesting characteristic of the concurrent deque implementation is that a processor can detect these boundary cases, e.g., determine whether the array is empty or full, without checking the relative locations of the two end pointers in an atomic operation.

Abstract: In a networked computer environment, a client is unencumbered from signature generating components, yet conversant to transmit signature-based documents in a signature-based metalanguage such as XML. The nonsigning client/user invokes a signature from a signature server to send a payload of data in a signed message format to a recipient also conversant in the metalanguage, according to the metalanguage format. The nonsigning client receives a signature block including a signature value from the server. The client identifies a payload for transmission according to the metalanguage. Employing the metalanguage interpreter in client, the client stores the payload data in the signature block without disrupting the signature and the data it covers in the signature block. The nonsigning client the sends the resulting signature message including the payload data and the signature value, in the metalanguage format, to the recipient destination conversant in the metalanguage.

Abstract: One embodiment of the present invention provides a system that facilitates faster execution of code on a memory-constrained computing device that has fast on-chip RAM, wherein the fast on-chip RAM is located on a processor chip, but is not cache memory. The system operates by copying a compiled method from an object heap to the fast on-chip RAM on the memory-constrained computing device. Additionally, the system updates an execution pointer to point to the compiled method in the fast on-chip RAM, wherein the execution pointer can also point to a compiled method in the object heap or an interpreted method in the object heap.

Abstract: A method and device divides a dividend by a divisor, the dividend and the divisor both being integers. The method and device determine a maximum possible number of quotient digits (NDQ) based on a number of significant digits of the divisor and the dividend, normalizes the dividend and divisor, and calculates NDQ number of quotient digits from the normalized divisor and dividend.

Abstract: Apparatus, methods, and computer program products are disclosed for concurrently searching a memory containing a skiplist data structure. The method locates the skiplist data structure in the memory. The skiplist data structure includes a plurality of linked lists related by a skiplist invariant. Furthermore, the plurality of linked lists includes a first-level linked list and one or more higher-level linked lists. The skiplist data structure also includes a plurality of nodes, each of which includes a key field, at least one pointer field, and a lock field, respectively. Each of the plurality of nodes is linked to the first-level linked list through the at least one pointer field and ordered responsive to the key field.

Abstract: A method for enhancing mobility of a subscriber in a telecommunications environment. The method includes deploying with a first network operator a service that is accessible by a subscriber via a first network. The method continues with creating a service detail record containing information related to an identity of the service, e.g., defining the service. The method then involves publishing the service detail record in a service registry that is accessible by a second network operator operating a second network. The second network operator receives over the second network a request from the subscriber for the service and in response, processes the service detail record and based on such processing provides the service to the subscriber via the second network. To provide the services, the service is executed on the first network using resources of the first network allocated to the service, such as by the service detail record.

Abstract: An authentication system includes a smart access card issued to a user, a client computer, a desktop authentication module configured to prevent a user from accessing resources of the client computer prior to successful completion of a two factor authentication; a card reader interface providing communication between the smart access card and the desktop authentication module; and an enrollment server for enrolling the access card into a server data store. The smart access card has an authentication credential comprising an authentication certificate and a card unique identifier. The enrollment server is in communication with the desktop authentication module via a network connection for receiving the authentication credential from the smart access card and performing two factor authentication for a user, the two factor authentication using the authentication credential prior to the enrolling.

Abstract: Disclosed herein is the creation and utilization of automated diagnostic agents that are used by service engineers to diagnose faults, errors and other events or conditions within a grid-based computing system, and provide a derived list of suspect root causes for the events. Related computerized processes and network architectures and systems supporting such agents are also disclosed. The automated diagnostic agents utilize software driven rules engines that operate on facts or data, such as telemetry and event information and data in particular, according to a set of rules. The rules engine utilize a neural network analysis environment to predict in accordance with the rules, facts and data found in the grid-based system to make probabilistic determinations about the grid. Particular memory allocations, diagnostic process and subprocess interactions, and rule constructs are disclosed.

Abstract: A hard disk drive bracket latch and release mechanism includes a lever arm attached to a hard disk drive bracket bezel rotatably between a closed position against the bezel and an open position apart from the bezel, and a locking mechanism including a wireform disposed in a release button. The lever arm includes a slotted end and spring. The wireform translates between a forced releasing position when the release button is depressed and a natural latching position otherwise. The wireform is shaped to bias the release button outward. The wireform fits into the slotted end of the lever arm in the latching position.