Abstract: Techniques for initialization of Java classes are disclosed. As such, the techniques can be implemented in a Java virtual machine to initialize Java classes represented in Java class files. A Java class loader suitable for loading class files into the Java virtual machine is disclosed. As will be appreciated, the Java class loader facilitates loading and execution of the Java initialization methods that need to be executed in order to initialize Java classes. Moreover, the Java class loader operates to remove the Java initialization methods after they have been executed and no longer serve a useful purpose. This means that the virtual machine can utilize its memory space more efficiently. As a result, the performance of virtual machines, especially those operating with limited resources is improved.

Abstract: Methods and apparatus for providing a progress associated with an executing process are disclosed. A progress report is generated in a progress reporting language, the progress reporting language indicating a progress of one or more steps in the executing process. The progress report is then provided to a user interface mechanism capable of interpreting the progress reporting language, where the user interface mechanism is adapted for generating a user interface indicating the progress of the one or more steps in the executing process. The user interface mechanism receives the progress report, ascertains the progress of the steps in the executing process from the progress report, and generates a user interface indicating the progress of the steps in the executing process.

Abstract: A floating point unit generates results in which status information generated for an operation is encoded within the resulting operand, instead of requiring a separate floating point status register for the status information. In one embodiment, a floating point operand data structure comprises a first portion having floating point operand data and a second portion having embedded status information associated with at least one status condition of the operand data. The status condition may be determined from only the embedded status information. The status condition may also be associated with at least one floating point operation that generated the operand data structure. The outcome of a conditional floating point instruction may be based on the embedded status information without regard to contents of the floating point status register.

Abstract: A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the floating point operand, receives one or more control input signals, determines one or more predetermined formats in which the plurality of operands are represented, and generates one or more control signals. The result assembler receives the control signals from the circuit, along with one or more inputs, and assembles a result.

Abstract: Provided is a method, system, and program for managing files in a file system. A plurality of files are provided in a primary storage used by an application program. A criteria is applied to determine files to release in the primary storage that have been copied to a secondary storage. A request is received for data from the application program in one file that was released and resides on the secondary storage. Data is read from the requested file in the secondary storage into a memory accessible to the application program. Data is provided from the file in the memory to the application program before the entire file has been read from the secondary storage into the memory.

Abstract: A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.

Abstract: Improved techniques for determining Java hashcode values for Java objects are disclosed. The techniques can be implemented to use a new Java Bytecode instruction which is suitable for execution by a Java virtual machine. As such, the new Java Bytecode instruction can be executed to determine Java hashcode value. Moreover, as will be appreciated, the Java hashcode values can be determined without invoking the Java method which is conventionally used to determine hashcode values. This means that the costly overhead associated with repeatedly invoking Java methods is avoided. In other words, operations that are conventionally performed each time this method is invoked need not be performed. As a result, the performance of virtual machines, especially those operating with limited resources (e.g., embedded systems), can be improved.

Abstract: A system for providing a copy of data at a point in time, has: a data storage device including a master store arranged to store blocks of data, at least one subsidiary store to store point in time copy data having blocks of data copied from said master store at a particular point in time, and a bitmap store associated with each the subsidiary store to store data indicating when a data block of the master store differs from a corresponding data block stored in the associated subsidiary store. Where more than one subsidiary stores and associated bitmap stores are provided, a controller may make different point in time copies in different subsidiary stores. A number of master stores may also be provided, each associated with a corresponding subsidiary store and a bitmap store. In this case, the controller may ensure that point in time copies of all the master stores are made at the same point in time. Data from a master store may be stored in a subsidiary store only when it is to be replaced in the master store.

Abstract: Methods and systems are provided for performing efficient association traversal operations in a Common Information Model (CIM) implemented environment. A CIM Object Manager creates and defines instance objects and corresponding association objects in a repository. The CIM Object Manager creates wrappers for each object that include reverse links that show the relationship from an object to any corresponding association objects. When a relationship request for a selected object is received by the CIM Object Manager, it performs an association traversal operation using the reverse links stored in the repository. The CIM Object Manager locates the target object's wrapper in the repository, and collects relationship information from the reverse links included within the wrapper. The collected relationship information is then passed to the entity that initiated the request. Accordingly, efficient association traversals may be performed, without having to traverse each instance of defined association objects.

Abstract: A system for providing a floating point division comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data within the second floating point operand respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the result of the division of the first floating point operand by the second floating point operand. Additionally, the results circuit provides resulting status embedded within the resulting floating point operand.

Abstract: Provided is a method, system, and program for managing files in a file system. Data is received for a file. The data for the file is stored in a plurality of segments. An index associated with the file indicating how the file data maps to the segments. An Input/Output request is received with respect to an address in the file. The index for the file is used to determine the segment having the requested address in the file. The determined segment including data at the requested address is then accessed.

Abstract: Testing of an electronic system is optimized by using a single set of sub-tests and varying the testing sequence to produce tests tailored for different purposes such as screening and diagnostic testing. For example, a programmable test sequencer in the electronic system responds to a test selection variable by using a first sequence of the sub-tests to optimize the testing process for screening and a second sequence of the sub-tests to optimize the testing process for diagnostic testing. In the diagnostic mode, the sub-tests are run so that each sub-test builds upon the previous sub-tests and uses previously-tested hardware to verify additional hardware. In the screening mode, the sub-tests are the same, but the execution order of the sub-tests is reversed so that more complex hardware is tested first as a screening mechanism.

Abstract: A CPCI system is adapted to reliably detect the presence of all front cards, whether hot swappable or not. The system includes a line that is used to detect the presence of a front card. The line is connected to a connector-pin of a slot. The line is also connected to a pull-up resistor so that when a front card is not inserted in the slot, the line has a high value. When a front card is inserted in the slot, the connector-pin mates with a corresponding connector-pin in the front card. The corresponding connector-pin is connected to a ground layer of the front card so that the line becomes grounded. The voltage level on the line is input to a register that outputs a high or low to a circuit for detecting the presence of a front card. The circuit may be a hot swap controller, a CPU or a status indicator. Accordingly, depending on the output of the register, the circuit reliably determines whether a front card is present in the particular slot.

Abstract: Programmable logic structures include logic blocks that operate at very low supply voltages. According to the invention, a pass transistor is positioned between logic blocks. Since the logic blocks of the invention operate at very low supply voltages, the pass transistor can be overdriven on, thereby reducing the added resistance. In one embodiment of the invention, the pass transistor is a low threshold transistor. In this embodiment, the pass transistor is also overdriven off to reduce leakage current and further isolate the logic blocks.

Abstract: An integrated circuit device includes first and second arrays of semiconductor dice. Each array of dice is arranged in face-to-face relation to the other array of dice, thus forming a lower layer of dice and an upper layer of dice. The layers are aligned so that each upper layer die straddles two or more of the lower layer dice, thus defining overlap regions. In the overlap regions, signal pads of one layer are aligned with corresponding signal pads of the other layer. The two layers are spaced apart, thus creating a capacitance-based communication path between the upper and lower layers via the signal paths.

Abstract: A method for reducing power supply noise in the power supply system of a delay locked loop has been developed. The method includes powering up a delay locked loop and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the delay locked loop.

Abstract: A single-input/dual output sense amplifier includes cross-coupled transistors connected to a reference voltage; a first input transistor and a second input transistor connected to the cross-coupled transistors, wherein the first input transistor is coupled to a single input bit-line and the second input transistor is coupled to a reference voltage; an inverter receiving the input bit-line signal and outputting a complement of the input bit-line signal; a control circuit coupled to the second input transistor and receiving the complement of the input bit-line signal, wherein the cross-coupled transistors produce dual differential outputs.

Abstract: A bus tuning system is provided for determining the configuration of an electronic device and for testing and tuning a bus system of the electronic device specifically for its configuration, the bus system including a bus interface coupled with a bus characterized by a number of parameters.

Abstract: A system for providing a floating point sum comprises an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data with the second floating point operand respectively. In addition, the system comprises a results circuit coupled to the analyzer circuit. The results circuit is configured to assert a resulting floating point operand containing the sum of the first floating point operand and the second floating point operand and a resulting status embedded within the resulting floating point operand.

Abstract: Use of a smart proxy as a wrapper around a stub in a distributed system. Instead of receiving a stub as a result of a remote procedure call, a caller receives a smart proxy including the stub as an embedded object. The smart proxy performs predefined processing associated with a remote procedure call, the processing possibly occurring before, during, or after a response to the call.