Abstract: A control memory is provided for storing the control and state information of a number of virtual direct memory access (DMA) channels. A control memory arbiter and a control memory data bus are also provided to arbitrate accesses to the control memory to facilitate asynchronous transmit and receive. Separate areas in the control memory are provided for storing the control and state information of the transmit DMAs, and the receive DMAs. Additionally, descriptive information about the transmit/receive data ring and its descriptor, the data packet being transferred and its cells are also stored for the transmit and receive DMAs. The control memory is also used to stored a programmable bandwidth group (BWG) table comprising a plurality of BWG index entries for bandwidth selection.

Abstract: An instruction decoder allows the folding away of JAVA virtual machine instructions pushing an operand onto the top of a stack merely as a precursor to a second JAVA virtual machine instruction which operates on the top of stack operand. Such an instruction decoder identifies foldable instruction sequences and supplies an execution unit with a single equivalent folded operation thereby reducing processing cycles otherwise required for execution of multiple operations corresponding to the multiple instructions of the folded instruction sequence. Instruction decoder embodiments described herein provide for folding of two, three, four, or more instruction folding. For example, in one instruction decoder embodiment described herein, two load instructions and a store instruction can be folded into execution of operation corresponding to an instruction appearing therebetween in the instruction sequence.

Abstract: A dispatch mechanism is provided for dispatching data units, (e.g. datagrams or packets) divided into one or more fragments, via a telecommunications network. The dispatch mechanism includes a queue for queuing fragments for transmission. It further includes a queue controller operable when a fill level of the queue exceeds a threshold value to discard fragments of data units for which a fragment has not already been queued and to add to the queue fragments of data units for which a fragment has already been queued. The dispatch mechanism maintains a record of data units which are to be transmitted (that is when one fragment of the data unit has already been passed for despatch) and a record of data units which are to be dropped (that is data units for which a fragment has already been dropped). The dispatch mechanism enables more effective use of network capacity by reducing the possibility of incomplete data units being transmitted over the network.

Abstract: A method and apparatus for delivering analog data on demand from a multiple channel digital media server are provided. A number of digital data streams are admitted to a media server. A number of control bits in the form of program packet identifiers are extracted from the admitted digital data streams. One of a number of channels in a converter is allocated as a control channel. A number of control commands are transmitted to the control channel for each of the converter channels in response to user selections, the control commands comprising the extracted program packet identifiers of the digital data streams. The admitted digital data streams are transmitted to the decoding channels of the converter where the converter channels convert the digital data streams to analog data streams in response to the extracted program packet identifiers.

Abstract: A method of implementing a scan flipp for use with logic gates includes configuring the flip-flop into a scan mode or data mode. Then the flip-flop enters the precharge phase in which a dynamic input stage is precharged and a static output stage maintains the output signal from the previous evaluation phase. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. During the evaluation phase in the scan mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the scan input signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.

Abstract: Systems and methods for programming applications with GUIs in accordance that do not require time-consuming and error-prone custom coding of GUI/internal variable synchronization routines, in general, and GUI/BO synchronization routines, in particular. An embodiment includes a plurality of classes for associating and synchronizing GUI components and BO attributes. The classes include: an inspector class, a selection class and a plurality of editor classes. The inspector class includes methods and data structures that enable a client application to bind a set of GUI components to the attributes of at least one business object. As a first step in associating and synchronizing GUI components and BO attributes a client application constructs an instance of the inspector class. The client application then passes the inspector instance a selection class instance that includes the business object(s) whose properties are to be synchronized with the GUI components.

Abstract: A remote monitoring system automatically communicates system diagnostic information from a monitored computer system to a remote service center at regular intervals. The remote monitoring system includes a plurality of monitored computers at a first location coupled together by a network. One of the monitored computers is a master and others of the monitored computers are slaves coupled to the master. The monitored computers store system diagnostic information resulting from execution of diagnostic programs. The diagnostic information from the slaves is collected at a memory location accessible by the master before the diagnostic information from all of the monitored computers is communicated to the remote monitoring computer at the second location. The remote monitoring computer receives the diagnostic information at predetermined intervals. The received diagnostic information is incorporated into a searchable database.

Abstract: A method and apparatus for shared memory management in a switched network element is provided. According to one aspect of the present invention, a shared memory manager for a packet forwarding device includes a pointer memory having stored therein information regarding buffer usage (e.g., usage counts) for each of a number of buffers in a shared memory. An encoder is coupled to the pointer memory for generating an output which indicates a set of buffers that contains a free buffer. The shared memory manager further includes a pointer generator that is coupled to the encoder for locating a free buffer in the set of buffers. The pointer generator is further configured to produce a pointer to the free buffer based upon the output of the encoder and the free buffer's location within the set of buffers.

Abstract: A fast frame buffer system and architecture supports preferably 24-bit capability and includes an integer rendering pipeline, especially useful for three-dimensional applications. The system includes a frame buffer random access memory system ("FBRAM") that includes video source data and is configurable as a single-buffer or double-buffer, a fast frame buffer controller integrated circuit ("FFB ASIC") that includes system command and video refresh control functions, and a random access memory digital-to-analog converter unit ("RAMDAC") that includes the buffer system timing generator. A FBRAM controller unit provides both parallel accelerated rendering pipeline and direct access paths to the FBRAM unit. The timing generator outputs serial clock and serial clock enable signals, the latter signal preceding horizontal blanking signals by preferably N=1 serial clock pulses to compensate for pixel signal path timing delays.

Abstract: Methods, apparatuses and products are provided for verifying the authenticity of data within one or more data files. Each data file is provided with an identifier, such as a one-way hash function or cyclic redundancy checksum. A signature file, that includes the identifiers for one or more data files, is provided with a digital signature created with a signature algorithm. The data file(s) and signature file are then transferred, or otherwise provided to a user. The user verifies the digital signature in the signature file using a signature verifying algorithm. Once verified as being authentic, the signature file can be used to verify each of the data files. Verification of the data files can be accomplished by comparing the identifier for each data file with the corresponding identifier in the signature file. If the identifiers in the data and signature files match, then the data file can be marked as authentic.

Abstract: A method and apparatus for publishing and receiving events to and from a network. A plurality of "publisher" entities publish information and a plurality of "subscriber" entities request and use the information. Publishers and subscribers are connected to each other through a network. The network is a "store and forward" network whose routing is "content-based." The basic quanta of information is called an "event." Publishers publish events and subscribers subscribe to events that match criteria defined by the subscriber. Publication and subscription are performed asynchronously. Publishers and subscribers do not have direct knowledge of each other. The system receives a published event from a publisher and routes the event to all appropriate subscribers. Each subscriber is guaranteed to receive all events published on the system if, and only it they match the subscription criteria specified by the subscriber.

Abstract: Systems and methods for increasing the execution speed of interpreted programs which utilize an operand stack are provided. The value for the top of the operand stack is stored in one or more registers. A state of the interpreter indicates the data type of the value for the top of the operand stack stored in the one or more registers. An interpreter may be generated that is both fast and efficient in terms of the memory required for the interpreter.

Abstract: A single transaction technique for a journaling file system of a computer operating system in which a single file system transaction is opened for accumulating a plurality of current synchronous file system operations. The plurality of current synchronous file system operations are then performed and the single file system transaction closed upon completion of the last of the file system operations. The single file system operation is then committed to a computer mass storage device in a single write operation without the necessity of committing each of the separate synchronous file system operations with individual writes to the storage device thereby significantly increasing overall system performance. The technique disclosed is of especial utility in conjunction with UNIX System V based or other journaling operating systems.

Abstract: A frequency difference detector includes a pulse generator that receives an NRZ signal and a reference signal and provides data pulses having first edges based on edges of the NRZ signal and second edges based on edges of the reference signal, a pulse router that routes consecutive ones of the data pulses to different signal paths, a voltage generator that receives the data pulses from the signal paths and provides voltage signals with amplitudes based on pulse widths of the data pulses, and a comparison circuit that receives the voltage signals and provides error pulses with amplitudes based on voltage differences between the voltage signals. The amplitudes of the error pulses represent a frequency difference between the NRZ signal and the reference signal. Preferably, the data pulses have leading edges based on edges of the NRZ signal and the lagging edges based on leading edges of the reference signal immediately following the edges of the NRZ signal.

Abstract: A network device such as an Asynchronous Transfer Method (ATM) device with a high level interrupt which begins processing a packet and transfers process control to a lower level software interrupt which completes the packet processing. Prior to the transfer of process control, the hardware interrupt generates a put information for the packet which is then retrieved and utilized by the software interrupt to process the packet. A unique generation number is assigned to each data stream generated for the packet. The generation number associated with a given packet's put information is compared to the generation number of a data stream to which the packet is destined to. If the generation numbers are equal, it is assumed that the data stream to which the packet is destined to has not been changed and the packet is forwarded to the data stream for further processing.

Abstract: A hypertext browsing system collects information about availability of links and display this link availability information. A user can then readily determine whether the target of a particular link may be followed. This increases the efficiency of user browsing in that time is not wasted in following unavailable links. Also, the hypertext browsing system may collect information about the titles of link targets and display this title information. The title information helps a user decide whether a particular link is worth following.

Abstract: A hardware virtual machine instruction processor directly executes virtual machine instructions that are processor architecture independent. The hardware processor has high performance; is low cost; and exhibits low power consumption. The hardware processor is well suited for portable applications. These applications include, for example, an Internet chip for network appliances, a cellular telephone processor, other telecommunications integrated circuits, or other low-power, low-cost applications such as embedded processors, and portable devices.

Abstract: Electromagnetic interference ("EMI") is reduced in a CRT video display system by spreading-out the EMI-producing spectra present in the video pixel data and/or clock signals. A clock dropping circuit coupled between the display generator main oscillator and the timing generator periodically phase-modulates the timing generator clock signal such that it comprises N phases, where N.gtoreq.2. As a result, each horizontal line of video data and the horizontal synchronization signals is phase shifted. This dual-shifting effect eliminates display image distortion that would result if only the video signal were shifted. Video distortion is further minimized by deriving the horizontal and vertical synchronizing signals from a common constant clock. EMI energy associated with each clock harmonic is spread by a frequency amount .DELTA.f proportional to the rate of phase change in the clock signal, the rate of phase change exceeding half the bandwidth f.sub.m of a standard EMI measurement reference window.

Abstract: An intuitive graphical user interface is based upon a geographic map structure, and includes a system for controlling remote external electronic devices. In the defined graphical user interface, each Space of the geographic map structure is rendered on a touch screen display as a graphic image of a geographic space. Within each Space are colored cartoon-like icons called "objects" which can be Selected and manipulated by the user. Certain objects, referred to as portals, transport the user from one Space to another Space when Selected. Other objects, referred to as buttons, perform associated actions or functions when Selected. The graphical user interface is displayed on a hand-held display device used to control remote devices. Each remote electronic device transmits a user interface program object that defines a graphical user interface to the display device.