Patents Assigned to Sun Microsystems
  • Patent number: 6003104
    Abstract: A CPU of a microprocessor includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU has a plurality of first ports coupled to respective first ports of the module units via dedicated buses therebetween and has a second port coupled to a first port of the common bus. The module units each include a second port coupled to respective second ports of the common bus. Communication between the module units is routed through and controlled by the BIU. To request a transaction, a module unit (the initiator) sends a request to the BIU via its dedicated bus to the BIU. The BIU arbitrates among present requests and, in response thereto, grants the arbitration winner's request and transmits a command to the target of the requested transaction. Preferably, both of these signals being are transmitted via the dedicated buses. Thereafter, data is routed from, for instance, the target, to the BIU via a corresponding dedicated bus.
    Type: Grant
    Filed: December 31, 1997
    Date of Patent: December 14, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Gunes Aybay, Sandeep Aggarwal, David Penry
  • Patent number: 6002771
    Abstract: The present invention provides a method and system for regulating discounts on merchandise distributed through networked computer systems. The method and system involve the use of discount coupons valid toward the repurchase of the merchandise. These discount coupons include mechanisms for verifying the validity of the coupons. A system in which the present invention operates includes a vendor computer system and a user computer system connected via a network. The vendor and user computer systems each include a computer connected to a display device, a keyboard, and a secondary storage device. A vendor discount regulator and a user discount regulator are stored in the vendor/user secondary storage devices for execution by the vendor/user computers. In operation, when a user desires to purchase merchandise, the user creates a request to purchase the merchandise and sends the request to purchase to a vendor.
    Type: Grant
    Filed: May 22, 1996
    Date of Patent: December 14, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Jakob Nielsen
  • Patent number: 5999978
    Abstract: An access control database defines access rights through the use of access control objects. The access control objects include group objects, each defining a group and a set of users who are members of the group, and rule objects. A first subset of the rule objects each specify a set of the group objects, a set of the management objects, and access rights by the users who are members of the groups defined by the specified set of the group objects to the specified set of management objects. The access control server responds to the access requests from the users by granting, denying and partially granting and denying the access requested in each access request in accordance with the access rights specified in the access control database. A second subset of the rule objects in the access control database each specify user access rights to event notifications generated by the specified set of management objects.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Rajeev Angal, Sai V.S. Allavarpu, Shivaram Bhat, Bart Lee Fisher
  • Patent number: 5999731
    Abstract: A program interpreter for computer programs written in a bytecode language, which uses a restricted set of data type specific bytecodes. The interpreter, prior to executing any bytecode program, executes a bytecode program verifier procedure that verifies the integrity of a specified program by identifying any bytecode instruction that would process data of the wrong type for such a bytecode and any bytecode instruction sequences in the specified program that would cause underflow or overflow of the operand stack. If the program verifier finds any instructions that violate predefined stack usage and data type usage restrictions, execution of the program by the interpreter is prevented. After pre-processing of the program by the verifier, if no program faults were found, the interpreter executes the program without performing operand stack overflow and underflow checks and without performing data type checks on operands stored in operand stack. As a result, program execution speed is greatly improved.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Frank Yellin, James A. Gosling
  • Patent number: 5999732
    Abstract: Techniques for reducing the cost of dynamic class loading and initialization checks in compiled code are provided. Virtual machine instructions are compiled into one or more native machine instructions even if required runtime execution information is unavailable at the time of compilation. The native machine instructions include placeholder data where the required runtime execution information should be. The native machine instructions are overwritten with a native machine instruction that transfers control to a section of code or stub that, at runtime execution, replaces the placeholder data with the required runtime execution information and execution continues.
    Type: Grant
    Filed: March 23, 1998
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Lars Bak, Srdjan Mitrovic
  • Patent number: 5999712
    Abstract: Cluster membership in a distributed computer system is determined by determining with which other nodes each node is in communication and distributing that connectivity information through the nodes of the system. Accordingly, each node can determine an optimized new cluster based upon the connectivity information. Specifically, each node has information regarding with which nodes the node is in communication and similar information for each other node of the system. Therefore, each node has complete information regarding interconnectivity of all nodes which are directly or indirectly connected. Each node applies optimization criteria to such connectivity information to determine an optimal new cluster. Data represent the optimal new cluster is broadcast by each node. In addition, the optimal new cluster determined by the various nodes are collected by each node. Thus, each node has data representing the proposed new cluster which is perceived by each respective node to be optimal.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Hossein Moiin, Ronald Widyono, Ramin Modiri
  • Patent number: 5999728
    Abstract: The present invention is directed to providing an ability to re-host, or port, an object oriented graphical user interface implementation from a native window-based platform, or environment, to another window-based platform, or environment. Exemplary embodiments abstract any notifications (e.g., events, state changes or "interests") which occur in the native environment as behavioral specifications. These behavioral specifications, (i.e., traits or protocols) can be used as part of a conformance negotiation to determine, during the execution lifetime of the graphical user interface, whether a particular client side object will conform with the behavioral specifications which have been abstracted from server side events associated with a different object. Where the conformance negotiation proves successful, abstract notifications can flow between particular instances of objects to model the state of the system, rather than using native implementations of events.
    Type: Grant
    Filed: July 30, 1996
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Laurence P. G. Cable
  • Patent number: 5999191
    Abstract: A central processing unit (CPU) is provided and is coupled to a display for displaying graphic and other data in multiple overlapping windows. The CPU is further coupled to one or more input devices which permits a user to selectively position a cursor and input and manipulate data within each of the windows on the display. The windows include defined areas having window features such as text, icons and buttons corresponding to functions to be executed by the CPU. Multiple applications may be executed concurrently by the CPU such that each application is associated with one or more windows. Each display element ("pixel") comprising the display is represented by multiple bits in a computer frame buffer memory coupled to the CPU. An alpha value (.alpha.) is associated with the intensity of each pixel of the display, such that multiple images may be blended in accordance with a predefined formula utilizing the alpha values.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc
    Inventors: Edward H. Frank, Patrick J. Naughton, James Arthur Gosling, John C. Liu
  • Patent number: 5999727
    Abstract: A system, apparatus and method which functions to restrain over-eager load boosting in an out-of-order processor through the implementation of a special "coloring" mechanism that colors dependent load and store instructions to ensure recognition of a dependency based on the assignment of a common multi-bit "color" scheme. In an exemplary embodiment, two bits of color are assigned to load and store instructions. These color bits are stored in a special array and are read when the load or store is read from the instruction cache ("I$"). The encoding of "00" for a load, for example, may indicate no coloring dependency for the load. Any encoding other than a "00" is utilized to indicate a store-load dependence for a store and load of the same color. The color bits for the load and store instructions are updated when a read-after-write ("RAW") hazard is detected by the memory disambiguation buffer ("MDB") for a store-load pair.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Ramesh Panwar, Ricky C. Hetherington
  • Patent number: 5999034
    Abstract: A circuit for controlling a voltage provided to a switching transistor in a voltage conversion buffer which drives a high voltage output with low voltage transistors. The circuit has two elements to it. First, a pull-up circuit pulls the gate of the switching transistor to a high voltage level in response to a first state of a control logic signal. Second, a pull-down circuit pulls the gate of the switching transistor down to an intermediate voltage in response to a second state of the control logic signal. The intermediate voltage is set to be less than the high voltage by no more than approximately the low voltage amount. The pull-down circuit is a transistor connected to a low voltage source, which limits the pull-down voltage. Additional transistors are provided to turn on and off the pull-down transistor, with a circuit connected to a fail-safe low voltage source being used to protect these transistors.
    Type: Grant
    Filed: January 28, 1998
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Gajendra P. Singh, Vidyasager Ganesan
  • Patent number: 5999404
    Abstract: An electronic system that may include an electronic card sub-module that is electrically connected to, and in fluid communication with, an electronic card module. The electronic card module can be mated with a motherboard and coupled to a manifold of a cooling system that provides a cooling fluid to the modules. The cooling fluid can flow directly onto integrated circuits or integrated circuit packages located within the modules. Each module may have an electrical connector and a fluid connector that allows the sub-module to be plugged into the module, and the module to be plugged into the motherboard and manifold without using any tools or hardware.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Vince P. Hileman
  • Patent number: 5999972
    Abstract: An interprise computing manager provides coordination between application programs by having each server program controlling the client executable program. In this manner, each client program communicates from the client to the server using a predefined protocol. A distributed computer system is disclosed with software for a client computer, a server computer and a network for connecting the client computer to the server computer which utilize an execution framework code segment configured to couple the server computer and the client computer via the network, by a plurality of client computer code segments resident on the server, each for transmission over the network to a client computer to initiate coupling; and a plurality of server computer code segments resident on the server which execute on the server in response to initiation of coupling via the network with a particular client utilizing the transmitted client computer code segment for communicating via a particular communication protocol.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Sheri L. Gish
  • Patent number: 5999147
    Abstract: A head-coupled display device for use in presenting electronically generated visual images to a viewer. The device includes a headpiece worn by a viewer, and an image display screen mounted in the headpiece for presenting electronically generated images. A fresnel lens is positioned adjacent the screen for focusing images from the screen at a selected position for viewing as a virtual image. The lens has a set of concentric converging rings whose surface curvatures act to minimize rectilinear distortion of the virtual images perceived by the viewer over the entire field of view of the image.
    Type: Grant
    Filed: November 28, 1997
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Michael A. Teitel
  • Patent number: 5999988
    Abstract: The method and apparatus for generating and employing a run-time generated stub to reference an object in an object oriented system. This method and apparatus represents in a first virtual machine a remote object implemented in a second virtual machine by employing a stub class. An object reference is sent by the second virtual machine and received by the first virtual machine. The object reference includes an interface descriptor that identifies the interface(s) of the remote object and an object handle that identifies the remote object. At run-time, the information associated with the remote object is transformed into a stub class that represents the remote object and implements only those interfaces identified by the interface descriptor and also defined by the first virtual machine. After the stub class is created, an instance of that stub class is generated and provided to the first virtual machine.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Eduardo Pelegri-Llopart, Graham Hamilton, Peter B. Kessler, James H. Waldo, Roger Riggs, Ann M. Wollrath
  • Patent number: 5999609
    Abstract: Communications and messaging in a Computer-Telephony (CT) system are assisted using an Electronic Call Request (ECR), a computer and network system construct that operates in place of a telephone call. An ECR is invoked and made a storage and communication entity in a computing and network environment in which the ECR is logged in a queue. The ECR in the form of a storage and communication entity navigates the telephone network under the direction of the caller who graphically manipulates the ECR using a graphical user interface (GUI). The ECR is activated into a telephone call at the command of a human or computer or network system agent generating a telephone call both to the caller and the call target.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Masahiko Nishimura
  • Patent number: 5999196
    Abstract: A 3-D graphics accelerator which includes a command block or preprocessor, a plurality of floating point processors or blocks, and one or more draw processors or blocks. The 3-D graphics accelerator includes a plurality of direct data channels or point-to-point buses, collectively referred to as the CF bus, which connect the command preprocessor to each of the plurality of floating point processors. The 3-D graphics accelerator also includes a plurality of direct data channels or point-to-point buses, collectively referred to as the FD bus, which connect the plurality of floating point processors to each of the draw processors. The system of the present invention also implements a bus from the command preprocessor directly to the draw processors, referred to as the CD bus, which uses portions of the above direct data channels. The CD bus shares or "borrows" the data lines from the CF bus and the FD bus and uses the floating point processors as buffer chips.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Shawn F Storm, Michael F. Deering
  • Patent number: 5998850
    Abstract: First and second semiconductor devices are separated by a field oxide on a semiconductor substrate, and a field plate is positioned over the field oxide. A leakage detector detects a field leakage current between the first and second semiconductor devices. A field plate generator tunes a potential of said field plate according to a magnitude of the field current detected by the leakage current detector. In this manner, field leakage is optimized, and total dose effects may be monitored for signs of device failure.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: December 7, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: James B. Burr
  • Patent number: 5996048
    Abstract: A cache architecture with a first level cache and a second level cache, with the second level cache lines including an inclusion vector which indicates which portion of that line are stored in the first level cache. In addition, an instruction/data bit in the inclusion vector indicates whether a portion of that line is in the instruction cache at all. Thus, when a snoop is done to the level two cache, additional snoops to the level one cache only need to be done for those lines which are indicated as present by the inclusion vector.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: November 30, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Rajasekhar Cherabuddi, Ricky C. Hetherington
  • Patent number: 5996075
    Abstract: A method and apparatus for fast and reliable fencing of resources such as shared disks on a networked system. For each new configuration of nodes and resources on the system, a membership program module generates a new membership list and, based upon that, a new epoch number uniquely identifying the membership correlated with the time that it exists. A control key based upon the epoch number is generated, and is stored at each resource controller and node on the system. If a node is identified as failed, it is removed from the membership list, and a new epoch number and control key are generated. When a node sends an access request to a resource, the resource controller compares its locally stored control key with the control key stored at the node (which is transmitted with the access request). The access request is executed only if the two keys match.
    Type: Grant
    Filed: November 2, 1995
    Date of Patent: November 30, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Vladimir Matena
  • Patent number: 5996056
    Abstract: An intermediate result signal arising from a manipulation of data signals is checked and reduced without using conditional branches, thereby improving instruction processing. Data signals are represented as signed 8-bit binary values in a two's compliment format. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. A processor operating under program control with the program has the following operations. The program determines whether the intermediate result signal is in a positive overflow state or a negative overflow state. A first mask signal is set to have 8 lower bits in an OFF position when the intermediate result signal is inside the range of a signed 8 bit integer. Otherwise, the first mask signal is set to have 8 lower bits in an ON position.
    Type: Grant
    Filed: June 24, 1997
    Date of Patent: November 30, 1999
    Assignee: Sun Microsystems, Inc.
    Inventor: Vladimir Y. Volkonsky