Abstract: According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting from a first signal a first plurality of bits of signal information to be processed, selecting from a second signal a second plurality of bits of signal information to be processed, reading the first plurality of bits of signal information into contiguous memory space so as to form a first word, reading the second plurality of bits of signal information into contiguous memory space so as to form a second word, causing a first logical AND operation to be performed on the second word with a mask, causing a first logical OR operation between the first word and the complement of the mask, causing a first EXCLUSIVE OR operation between the first word and the complement of the second word, causing a second logical AND operation between the results of the first EXCLUSIVE OR operation and the complement of the mask, subtracting the results of the first logical AND operati

Abstract: A method and apparatus for performing client-sensitive DNS translations includes the steps of receiving a translation request by a DNS server. The DNS server examines the translation request to determine if a record exists within the DNS server that associates the symbolic name included in the translation request with an IP record. If such a record exists, the IP address is returned as the translation. If not, the DNS server determines whether reflective client-sensitive translation is required. In the affirmative case, the request is reflected to back to the client where client-sensitive translation is performed and returned to the DNS server. If client-sensitive translation is not required, the DNS server determines whether non-reflective client-sensitive translation is required. If so, the requested translation is forwarded to a special DNS server, along with information that identifies the client system requesting translation.

Abstract: The cluster configuration database is a distributed configuration database wherein a consistent copy of the configuration database is maintained on each active node of the cluster. Each node in the cluster maintains its own copy of the configuration database and configuration database operations can be performed from any node. Configuration database updates are automatically propagated to each node in a lock-step manner. If any node experiences a failure, the configuration database uses a reconfiguration protocol to insure consistent data in each node of the cluster. The cluster configuration database uses a two-level consistency update framework to insure consistent data among the nodes. Each local configuration database uses a self-contained consistency record to uniquely identify and stamp each copy of the configuration database. The consistency of each individual copy of the configuration database can be verified from the consistency record.

Abstract: A system for generating a "where graph" for a parallel processing system comprising a parallel processing array controlled by a control processor. The processing array comprises a plurality of processing elements each processing a program comprising a main routine and a plurality of subroutines, the main routine calling at least one subroutine and at least some of said subroutines calling others of said subroutines. The control processor determines a consolidated program routine sequence identifying sequences of routines extending from said main routine to a current routine being processed by said at least some of said processing elements and generates and displays, on, for example, a video display, the program routine sequence in graph form. The graph comprises a plurality of graph nodes, each representing a routine, with the graph nodes being interconnected to depict the consolidated program routine sequence.

Abstract: A first computer sends a sequence of messages to a second computer using remote write operations to directly store each message in a corresponding memory location in the second computer, without performing remote read operations to confirm storage of each message in the second computer's memory. The first computer detects message transmission errors, if any, during the transmission of each message to the second computer and when a message transmission error is detected, resends the message to the second computer. The first computer also sends trigger messages to the second computer to prompt the second computer to process messages stored in the second computer's memory. The second computer processes each received message and uses a remote write operation to store an acknowledgment message in a corresponding memory location in the first computer.

Abstract: A read system for a multi-ported register file includes a segmented bit line coupled to a global bit line. Each local bit line segment is coupled to a sub-set of the register files in a column to reduce device load and interconnect wire load. The local bit line segments are each coupled to the global bit line by a local sense amplifier. Both the local bit line segments and global bit line are precharged prior to sensing a bit so that the local sense amplifiers do not require output pull-up transistors.

Abstract: In a computer graphics windowing system including a color map, a method for managing palette color value contents of the color map. Input color values are received. Error values between each input color value and each palette color value are used to determine a closest palette color value to each input color value. A list of input color values having largest error value distances to their respective closest palette color values is determined. A subset of this list is added to the color map to derive a modified color map. A color value metric process for determining an error value between each input color value and each palette color value comprises converting each input color value and each palette color value to a uniform color space. A lightness weighting constant is used to skew the error value in to be more strongly influenced by differences in lightness than by differences in chromaticity. A look up table having address spaces indexed by RGB index color values is generated.

Abstract: A CPU includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU includes a decode stage, an arbitration stage, and a control stage. Incoming requests asserted by the CPU module unit are provided to the BIU decode stage which, in response thereto, determines the type of transaction requested, the initiator module unit, and the target module unit. If the target identified in the decoded request is ready to accept a command, the decode stage forwards the request to the arbitration stage. The arbitration stage arbritrates amoung the present requests asserted by the module units and, in response thereto, alerts the control stage as to which of the module units has won the arbitration. The control stage decodes the request corresponding to the module unit that won the arbitration to determine the transaction type and target unit.

Abstract: An apparatus and method for resetting a dynamic logic circuit is disclosed. The apparatus includes an input circuit coupled to a plurality of input nodes wherein the input circuit comprises a plurality of FETs connected between a first voltage node and a dynamic node of a logic circuit. The gate electrode of each input circuit FET is connected to one of the input nodes. Precharged FET is connected between the dynamic node and a second voltage node. The precharge FET is configured to conduct a current for precharging the dynamic node to a predetermined voltage. An inverter is coupled between the dynamic node and an output node. A precharge control circuit is connected in a feedback path between the output node and the precharge FET. The precharge control signal activates the precharge control FET in response to a RESET pulse width and deactivates the precharge FET in response to the voltage on the dynamic node.

Abstract: Disclosed is a system for assisting in preventing over heating of the internal electrical components of a computer in the event of a failure of one of the adjacent fans of an array of fans employed to circulate cooling air over the components. The fans include openings through which air is forced from their inlet sides to their outlet sides. The system includes a vent for each fan arranged adjacent to and aligned with the fan opening at its outlet side. The vents are open and closed by vanes, having hinged slats construction to allow them to fall downwardly by their own weight or additional assistance. The vanes are kept open by the airflow created by the fans. Upon the failure of a fan, the absence of airflow through the opening thereof allows the slats of the vane to drop to close off the fan opening and prevent airflow into the fan opening from its outlet side.

Abstract: An IC includes a plurality of functional blocks each having a discrete block-level architecture. The functional blocks are connected to one another via metal interconnect lines defined by an interconnect architecture. One or more of the functional blocks includes a spare (i.e., unused) repeater amplifier. Where a repeater amplifier inserted in a particular long line of the interconnect structure would decrease the signal propagation delay through the long line, the interconnect architecture is modified so that the long line is routed through the spare repeater amplifier. Such modification decreases the signal propagation delay of the long line without requiring a modification of the block-level architecture.

Abstract: An absorbent pair refrigeration system comprising a source of liquid refrigerant; an evaporator for transforming the liquid refrigerant into vapor refrigerant at a lower temperature than the liquid refrigerant to thereby provide a desired cooling effect; a volume of absorbent in communication with the evaporator, wherein the vapor refrigerant is absorbed onto the absorbent; an electromagnetic wave generator for desorbing the vapor refrigerant from the sorbent without appreciably heating the absorbent; and a condenser in communication with the absorbent for condensing the vapor refrigerant which has been desorbed from the absorbent.

Abstract: One embodiment of the present invention provides a method and an apparatus for decoding a variable length code using lookup tables. This embodiment improves lookup performing by allowing multiple symbols to be retrieved in a single lookup, and allowing lookups into different tables to proceed in parallel. Another embodiment of the present invention provides for multiple secondary lookup tables to be selected based upon a prefix value decoded by a primary lookup table. Thus, one embodiment of the present invention can be characterized as an apparatus for decoding a variable length code. This apparatus includes an input from an encoded bitstream, the input including a first set of bits and a second set of bits. This apparatus also includes a first table indexed by the first set of bits, which includes entries containing decoded symbols corresponding to variable length codewords in the first set of bits.

Abstract: A method for enabling an application program to communicate with a network server, includes the steps of downloading a document from a document server to the application program, downloading code from a code server associated with the document server to the application program, the code including a network protocol handler for the network server, and using the network protocol handler to communicate with the network server.

Abstract: A digital computer includes an efficient mechanism by which an exception handler can traverse the instruction stream in a reverse direction to identify the instruction which gave rise to the exception condition after a discontinuity in an instruction stream. The digital computer is provided with both a program counter and an "old program counter." For points in an instruction sequence at which a discontinuity may occur, the "branch taken" portion of the instruction stream is provided with a predetermined type of instruction to enable the old program counter to be saved in a predetermined location. When the instruction is executed, the old program counter will contain a pointer to the "branch not taken" portion of the instruction sequence.

Abstract: A clock circuit for selectively enabling a clock signal to be propagated, via a transmission line, to an option module when the module is coupled to the clock circuit, and for preventing propagation of the clock signal through the transmission line when the option module is decoupled from the clock circuit. The clock circuit includes a clock driving element employed within a first module and a clock receiving element employed within a second module. The clock driving element includes a clock driver, normally an amplifier connected to at least one emitter-follower transistor. A pull-up resistor is coupled to the emitter of the transistor so that, when the option module is decoupled from the transmission line, the pull-up resistor applies voltage sufficient to turn-off the transistor. Otherwise, the pull-up resistor has no effect on the clock circuit.

Abstract: Systems and methods for implementing an execution stack which stores frames for functions written in multiple programming languages are provided. The frames for functions written in different programming languages may be interleaved on the same execution stack. A data block on the execution stack may be utilized to traverse the execution stack around a frame by storing a stack pointer and frame pointer to a previous frame. Additionally, exceptions may be propagated, with conversion if necessary, through frames on the execution stack that are written in different programming languages.

Abstract: An approach for allocating a set of virtual registers to a set of physical registers using selective spilling is described. A set of code and a spill variable are specified. A code region hierarchy containing a set of code regions is determined based upon the set of code. The first level of the code region hierarchy is evaluated and if the spill variable is referenced in more than one code region, code for performing a spill operation on the specified spill variable is added to the set of code based upon a code region which defines the specified spill variable. In addition, code for performing a reload operation on the specified spill variable is added to the set of code based upon code regions that use the specified spill variable.

Abstract: A stack management unit includes a stack cache to accelerate data retrieval from a stack and data storage into the stack. The stack management unit also includes an address pipeline to transfer multiple data words by a spill control unit and a fill control unit in the stack management unit. The address pipeline contains an incrementor/decrementor circuit, a first address register and a second address register. An address multiplexer drives either the output signal of the incrementor/decrementor or a cache bottom pointer to the first address register. The output terminals of the first address register are coupled to the input terminals of the second address register. A stack cache multiplexer drives either the address in the first address register or the address in the second address register to the stack cache. A memory multiplexer drives either the address in the address multiplexer or in the first address register to a slow memory unit.

Abstract: A variety of methods, apparatus, and data structures for managing transient and persistent distributed objects are disclosed. Objects for use as object references are described, both for transient and persistent objects. In one aspect of the invention, a data structure that is intended for use as an object reference for a transient object is disclosed having a set of endpoint addresses, an incarnation number, and an object key. These elements serve to uniquely identify and locate the transient object. In another aspect of the invention, an object that is intended for use as an object reference for a persistent object is disclosed having a host computer name, a locator identification, an object key, and a subobject identifier. The first three elements serve as an indirection to the persistent object and the third element is for use by the persistent object. These data structures enable a distributed object operating environment which integrates both transient and persistent objects.