Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: An apparatus for cooling an electrical component is disclosed which comprises a sorber containing a sorbent; a condenser in fluid communication with the sorber; an evaporator in fluid communication with both the sorber and the condenser and connected in heat-exchange relation to the electrical component; wherein a sorbate which has been condensed in the condenser is evaporated in the evaporator, thereby absorbing heat from the electrical component, and then adsorbed onto the sorbent; an electromagnetic wave generator; a waveguide coupler for directing the electromagnetic waves to the sorbent; wherein the sorbate is desorbed from the sorbent by the electromagnetic waves and condensed in the condenser; and wherein the desorption of the sorbate from the sorbent is substantially isothermal.

Abstract: Apparatus, methods, systems and computer program products are disclosed describing processes that optimize generational garbage collection techniques in a card-marked heap. The invention localizes nodes in an older generation that have a pointer to a newer generation. This node localization increases the density of such nodes in the cards marked as having these nodes and thus reduces the number of marked cards that need to be examined for nodes having pointers to the newer generation.

Abstract: A read system for a multi-ported register file includes a segmented bit line coupled to a global bit line. Each local bit line segment is coupled to a sub-set of the register files in a column to reduce device load and connection load. The local bit line segments are each coupled in series by local sense amps with the local bit line segment coupled to the input of a global sense amplifier. The number of cells coupled to the last bit line segment is more than the number of cells coupled to a bit line segment farthest from the global sense amplifier to balance device and interconnect load and provide for uniform read timing. Both the local bit line segments and global bit line are precharged prior to sensing a bit so that the local sense amplifiers do not require output pull-up transistors. This scheme will not work if the local sense amp includes a pull-up PMOS transistor at its output.

Abstract: The present invention provides a stack management unit including a stack cache to accelerate data transfers between the stack-based computing system and the stack. In one embodiment, the stack management unit includes a stack cache, a dribble manager unit, and a stack control unit. The dribble manager unit includes a fill control unit and a spill control unit. Since the vast majority of memory accesses to the stack occur at or near the top of the stack, the dribble manager unit maintains the top portion of the stack in the stack cache. Specifically, when the stack-based computing system is pushing data onto the stack and a spill condition occurs, the spill control unit transfers data from the bottom of the stack cache to the stack so that the top portion of the stack remains in the stack cache.

Abstract: A 3-D graphics accelerator for performing lighting operations using operands within a given fixed point numeric range. The 3-D graphics accelerator includes a first computational unit which is configured to compute a value of an attenuation factor usable for performing said lighting operation for local lights. The attenuation factor is represented in floating point format. The first computational unit is also configured to represent the attenuation factor in an intermediate format including a first intermediate value (a scaled attenuation factor value within the given fixed point numeric range), and a second intermediate value (a shift count usable to convert the scaled attenuation factor value back to the original attenuation factor value). The 3-D graphics accelerator further includes a lighting unit coupled to said first computational unit. The first computational unit is further configured to convey the intermediate representation of the attenuation factor to the lighting unit.

Abstract: An interprise computing manager in which an application is composed of a client (front end) program which communicates utilizing a network with a server (back end) program. The client and server programs are loosely coupled and exchange information using the network. The client program is composed of a User Interface (UI) and an object-oriented framework (Presentation Engine (PE) framework). The UI exchanges data messages with the framework. The framework is designed to handle two types of messages: (1) from the UI, and (2) from the server (back end) program via the network. The framework includes a component, the mediator which manages messages coming into and going out of the framework.

Abstract: An access control database has access control objects that collectively store information that specifies access rights by users to specified sets of the managed objects. The specified access rights include access rights to obtain management information from the network. An access control server provides users access to the managed objects in accordance with the access rights specified by the access control database. An information transfer mechanism sends management information from the network to a database management system (DBMS) for storage in a set of database tables. Each database table stores management information for a corresponding class of managed objects. An access control procedure limits access to the management information stored in the database tables using at least one permissions table. A permissions table defines a subset of rows in the database tables that are accessible to at least one of the users.

Abstract: An apparatus for cooling an electrical component is disclosed which comprises a sorber containing a sorbent; a condenser in fluid communication with the sorber; an evaporator in fluid communication with both the sorber and the condenser and connected in heatexchange relation to the electrical component; wherein a sorbate which has been condensed in the condenser is evaporated in the evaporator, thereby absorbing heat from the electrical component, and then adsorbed onto the sorbent; an electromagnetic wave generator; a waveguide coupler for directing the electromagnetic waves to the sorbent; wherein the sorbate is desorbed from the sorbent by the electromagnetic waves and condensed in the condenser; and wherein the desorption of the sorbate from the sorbent is substantially isothermal.

Abstract: A computer system including a highly efficient forced air cooling subsystem is disclosed. The computer system includes an enclosure having a first (e.g., front) panel, a processor mounted upon a motherboard located within the enclosure, and a fan located within the enclosure for providing a flow of air through the enclosure. The fan draws air into the enclosure through an opening (e.g., an intake vent) in the first panel and produces a pressurized stream of air. The fan may be oriented such that the pressurized stream of air is directed toward the processor. The computer system may also include a plenum adjacent to the first panel, wherein the intake vent allows ambient air surrounding the enclosure to enter the plenum. The fan may be mounted within an opening in a wall of the plenum. The enclosure may also include a second (e.g., rear) panel opposed to the first (e.g., front) panel and having three openings (e.g., exhaust vents) therein.

Abstract: A method and apparatus for dithering for color computer display systems includes the addition of a noise component to each of the color components of each pixel in a pseudo-random manner. The noise component is preferably different for each color component. Taking the image as a whole, the noise component repeats on a regular basis but is preferably selected so as not to repeat on adjacent pixels. The image is divided into squares of pixels and the same noise component is added to each of the same relative pixels from square to square. The preferred square of pixels is four pixels wide by four pixels high. The value of the noise component is chosen such that the most significant bit alternates both horizontally and vertically from pixel to pixel within the square of pixels.

Abstract: A method of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services I placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.

Abstract: A method and apparatus for converting a source executable code generated for execution on a source processor into a target executable code for execution on a target processor is provided. Typically, the following sequence of steps are performed on a computer for each instruction in the source executable code. Initially, a source instruction is selected from the source executable code. This source instruction typically has an opcode and one or more corresponding parameters used by the opcode during execution. Next, the source instruction opcode is used to isolate one or more corresponding parameters within the source instruction. After this is completed, one or more target instructions associated with the target processor are located which correspond to the source instruction. Then, a target instruction is generated by filling the one or more parameters isolated from the source instruction into the corresponding parameter locations in the one or more target instructions.

Abstract: An apparatus for cooling an electrical component is disclosed which comprises a sorber containing a sorbent; a condenser in fluid communication with the sorber; an evaporator in fluid communication with both the sorber and the condenser and connected in heat-exchange relation to the electrical component; wherein a sorbate which has been condensed in the condenser is evaporated in the evaporator, thereby absorbing heat from the electrical component, and then adsorbed onto the sorbent; an electromagnetic wave generator, a waveguide coupler for directing the electromagnetic waves to the sorbent; wherein the sorbate is desorbed from the sorbent by the electromagnetic waves and condensed in the condenser; and wherein the desorption of the sorbate from the sorbent is substantially isothermal.

Abstract: A turnstile FIFO stores data packet from each of a number of separate ordered sets in a generally circular list structure. A select data packet can be dequeued if no older data packet of the same ordered set is stored in the turnstile FIFO. The data packets are stored in the turnstile FIFO in a globally sequential order such that older data packets precede younger data packets regardless of membership in the one or more ordered sets. Turnstile logic determines whether the selected data packet is the oldest data packet of a given ordered set by determining set membership of all older data packets stored in the turnstile FIFO. Older data packets are stored in positions within the turnstile FIFO which precede the position of the selected data packet.

Abstract: A technique for eliminating the performance penalty of implementing jump instructions in a deeply pipelined processor includes a pipeline having a signal for indicating that the top of the address return stack has been updated by an address moved to the return register. An instruction moving a previously computed jump target address to the return register is included in code to be executed. The pipeline uses the instruction at the top of the RAS as a guess of the target instruction of a fetched jump instruction and immediately begins fetching instructions indicated by the guess.

Abstract: The present invention provides a method and apparatus that permits the introduction of customized compositing techniques into an application by a developer. A Composite interface and a CompositeContext interface are defined. Custom compositing operations can be defined by implementing these interfaces. A Composite object provides a CompositeContext object that holds the state and performs the compositing work. Multiple CompositeContext objects can be created from one Composite object to maintain separate states in a multi-threaded environment. An object implementing the Composite interface can be set as rendering state on a graphics object that provides rendering methods. This allows arbitrary compositing rules to be used by a developer. In one implementation of the Composite and CompositeContext interfaces, an AlphaComposite class is defined.

Abstract: A heat transfer apparatus is disclosed. The heat transfer apparatus includes a heat pipe containing heat transfer liquid. Disposed in the heat pipe is a centrifugal rotor assembly having fixed magnets on the rotor blades. A magnetic field is generated by a magnetic coil assembly that surrounds the heat pipe. The rotor assembly rotates in response to the magnetic field, agitating the heat transfer liquid. A second embodiment is a liquid heat transfer system that includes a heat absorption chamber, a pump, and a heat exchanger where circulation and cooling of the heat transfer liquid occurs outside of the heat absorption chamber.

Abstract: A method and apparatus for controlling a graphical array of buttons in a graphical user interface. The method and apparatus models the buttons as nodes of a network and depending on pre-determined criteria and establishes links between nodes. The presence or absence of links between nodes sets status relationships between them. The selecting by a user of one button will change/maintain the status of other buttons depending on links or absence of links between corresponding nodes. When a sufficient number of buttons are selected, the user may initiate a task utilizing the status of the buttons.

Abstract: A task scheduling computer program retrieved from a server computer system through a computer network and executed by a client computer system which can be a network computer having no persistent, writeable storage. In executing the task scheduling computer program, a collection of one or more execution schedules are retrieved. The collection of execution schedules can be retrieved from the client computer system, from the server computer system, or from another computer system coupled to the client computer system through the computer network. The collection can be uniquely identified within the computer network by a universal resource locator (URL). Each execution schedule of the collection specifies one or more execution times and a task to be performed by the client computer system at the one or more execution times. For each of the one or more execution schedules, the client computer system performs the specified task at the one or more execution times.