Abstract: In a processor executing instructions speculatively or out-of-order, an apparatus for tracking traps, exceptions, and interrupts within the processor. A table stores front-end and back-end traps associated with an instruction, and an instruction retirement module retires the instructions in order if no traps were associated with older instructions in the processor. In this way, the proper trap sequence of events is maintained so that traps can be properly handled.

Abstract: Apparatus, methods, systems and computer program products are disclosed describing a data structure and associated processes that optimize garbage collection. The invention sections a card vector associated with a card marked heap into portions. Each portion can be individually write protected. A section vector contains section data structures that are used to control their respective portions. When a write-barrier executes and attempts to mark a card marker in a read-only portion of the card vector, the invention traps the mark operation, sets the portion to read-write, changes the status of the section data structure and completes the mark operation. When a garbage collection phase scans the heap during the garbage collection process, it skips over portions of the card vector associated with sections having a read-only status--thus, improving the garbage collection process.

Abstract: A network system dynamically controls data flow between physical links by logically combining multiple physical links into a single logical channel trunk, preferably to balance data flow carried by each link. Each link in the trunk has identical physical layer and identical media access control layer characteristics. A system server assigns a single media access control layer address to the single trunked logical channel, preferably randomly by hashing destination media access control layer addresses for the links. The system server includes, in addition to a physical layer and a network layer, a pseudo-driver software layer disposed therebetween, which pseudo-driver software layer functions as a multiplexer in a receive path and functions as a de-multiplexer in a transmit path. The resultant preferably Ethernet-compatible network system operates in full-duplex mode and distributes packets from the server to the links to preserve temporal order of data flow.

Abstract: When a client computer requests data from a disk or similar device at a server computer, the client exports the memory associated with an allocated read buffer by generating and storing one or more incoming MMU (IMMU) entries that map the read buffer to an assigned global address range. The remote data read request, along with the assigned global address range is communicated to the server node. At the server, the request is serviced by performing a memory import operation, in which one or more outgoing MMU (OMMU) entries are generated and stored for mapping the global address range specified in the read request to a corresponding range of local physical addresses. The mapped local physical addresses in the server are not locations in the server's memory. The server then performs a DMA operation for directly transferring the data specified in the request message from the disk to the mapped local physical addresses.

Abstract: A system and method is disclosed that provides persistent capabilities for distributed, object-oriented applications running on generally available hardware. The disclosed system and method operate in a transparent distributed object system where inter-process messaging between the program objects is effected by paired transport managers, proxies and matched in-table and out-table slots. Each object needing to communicate with an object in another address space does so by transparently issuing messages to that object's local proxy. Each process provides a registrar that includes a secret code table wherein an object is registered with a unique, practically unguessable secret code. Anticipating the need to re-establish object-proxy links following a inter-process communications fault, proxies are made revivable, meaning that their links with corresponding remote objects can be revived following a communications interruption.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: An application binary interface includes linkage structures for interfacing a binary application program to a digital computer. Virtual address spaces are allocated for processes respectively. Page table entries for translation of the virtual address spaces into physical addresses are not removed as processes terminate, but only after all virtual address spaces have been allocated.

Abstract: The present invention is directed to a coaxial waveguide applicator for an electromagnetic wave-activated sorption system which comprises at least one sorber having a metallic tubular housing defining an outer conductor and first and second ends which are sealed to define an enclosure within the outer conductor; a sorbate/sorbent compound located within the enclosure; the sorber including a port through which a sorbate may be communicated into or out of the enclosure; a metallic inner conductor extending into the outer conductor and parallel to the longitudinal axis of the sorber; an electromagnetic wave generator; and a waveguide for coupling electromagnetic waves generated by the electromagnetic wave generator to the inner and outer conductors; wherein electromagnetic waves transmitted by the electromagnetic wave generator are propagated through the enclosure by the inner and outer conductors to desorb the sorbate from the sorbate/sorbent compound.

Abstract: A system and method are disclosed for rendering devices on a cluster globally visible, wherein the cluster includes a plurality of nodes on which the devices are attached. The system establishes for each of the devices in the cluster at least one globally unique identifier enabling global access to the device. The system includes a device registrar that creates the identifiers and a global file system. The identifiers include a globally unique logical name by which users of the cluster identify the device and a globally unique physical name by which the global file system identifies the device. The registrar creates a one-to-one mapping between the logical name and the physical name for each of the devices. The system also includes a device information (dev.sub.-- info) data structure maintained by the device registrar that represents physical associations of the devices within the cluster. Each association corresponds to the physical name of a device file maintained by the global file system.

Abstract: A voltage bias generator circuit which uses a series of small transistors to form essentially a resistor ladder to produce a desired bias voltage at an intermediate node using the sizing of the transistors and the placement of the node. The output node is then connected to a first voltage level shifting circuit for shifting the voltage by at least 1 V.sub.T. The output of the first voltage level shifting circuit is then coupled to the second voltage level shifting circuit, which shifts it back down or up to the desired bias voltage.

Abstract: An object's Z-buffered primitives are determined using a floating point Z=wF/W, where wF is the value the W coordinate achieves at the front clipping plane F. This representation produces Z-values ranging from 1 to .apprxeq.0 as W varies from W=wF to W.fwdarw..infin.. Z-values for distances near the back clipping plane advantageously have leading zeros and are more amenable to floating point representation and exhibit less information loss. Primitive vertices are examined and the largest vertex floating point exponent is stored and associated with the entire primitive as that triangle's floating point Z exponent. The stored exponent is subtracted from all the vertices' exponents and the results converted to fixed point, which format advantageously typically has few or no leading zeroes.

Abstract: A system and method for tracing device drivers using a computer is described. A memory is interconnected with a processor in the computer and configured into a user memory space and a kernel memory space. An application process executes on the processor within the user memory space. An operating system kernel executes on the processor within the kernel memory space with a traced device driver. A tracing device driver executes on the processor within the kernel memory space and is interposed between the application process and the traced device driver to trace interactions occurring between the traced device driver and the application process and the kernel operating system. A tracing process executes on the processor within the user memory space and interfaces with the tracing device driver. The tracing process controls the tracing device driver in accordance with user-specified parameters and includes a display for result sets generated by the tracing device driver.

Abstract: A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture efficiently executes software code by providing the processor with a grouper circuit which receives software code instructions from a secondary memory and groups these instructions based upon the content of the instructions and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set.

Abstract: In accordance with the present invention a method for modifying a sequence of instructions to improve memory management within a storage device during execution of the instructions, comprises the steps, performed by a processor, of (a) analyzing the sequence of instructions for a conflict indicating an undeterminable variable type, (b) determining the type of conflict, and (c) modifying the sequence of instructions to eliminate the conflict based on the determination.

Abstract: A light indicating apparatus for video conferencing provides a light that casts a shadow in a field of view of the video camera but provides light in an area surrounding the field of view to alert video conferencing participants when they leave the video camera's field of view.

Abstract: A method and apparatus for establishing and maintaining complex security rules is provided. The security rules are established through the use of "permission" classes that take advantage of the power and simplicity various features of object oriented programming, including the ability to inherit attributes and methods. For example, a permission super class is established that defines an interface to a validation method. A permission subclass may then be created which provides an implementation of the validation method. When invoked, the validation method indicates whether a given permission represented by one object belonging to a permission class encompasses the permission represented by another object belonging to a permission class. Classes are also provided for grouping permissions into sets, and for establishing protection domains for classes of objects.

Abstract: A system and method for tracking dirty memory which, in one embodiment, comprises a first memory corresponding to a first processor, a second memory corresponding to a second processor and a third memory coupled to the first memory, wherein the third memory stores bits corresponding to the pages of the first memory, and wherein each bit is set to "dirty" when the first processor writes to the corresponding page of the first memory and is set to "clean" when the corresponding page of the first memory is copied to a corresponding page of the second memory. The system and method can be used in a computer having multiple cpusets to assist in cpuset re-integration by copying the contents of one cpuset's memory to another cpuset's memory while the operating system of the computer continues to run.

Abstract: A system for a live applet or application development environment includes software that cooperatively promotes and permits immediate socialization of new components with existing components as the new components are instantiated or dropped onto the development desktop. This is achieved by registering a new component being instantiated with the development environment's kernel. Registration, in turn, invokes an initialization method derived from the class template that yielded the new component. The initialization method appropriately personalizes the new component when it executes its associated logic. The initialization method provide an editor for the new component if its properties are to be made editable. The software environment, its kernel, templates, components, editor and methods are preferably programmed in the Java programming language or a Java compatible language.

Abstract: A system for reducing query traffic in multi-processor shared memory system utilizes the inclusion of an unshared bit in translation table entries in the address translation system. A query system does not generate queries when the unshared bit indicates that the data has not been shared between the processors.