Abstract: In a computer network where remote user stations retrieve information from other sites in the network, a method and apparatus for creating and displaying dynamic link labels in a browser program operating on a remote user station. The link labels are created in an application program which can be run within the browser, and the link labels are designed to operate, at a minimum, in a similar manner as HTML hyper links. The link labels can also dynamically change in response to user input into the browser. For instance, the URL (Uniform Resource Locator) address or the text or appearance of the link label can change. Also, parameters based on user input can be formed by the application and used to form or alter other link labels.

Abstract: A output driving circuit having an output driving element, an overshoot protection mechanism, and an undershoot protection mechanism. When the overshoot protection mechanism senses an overshoot voltage at the output terminal of the output driving element, it raises the voltage at the control terminal of the output driving element. This serves to maintain the voltage between the output terminal and the control terminal of the output driving element within a safe range, thereby preventing overstress or damage to the element. When the undershoot protection mechanism senses an undershoot voltage at the output terminal of the output driving element, it lowers the voltage at the control terminal of the output driving element. This serves to maintain the voltage between the output terminal and the control terminal of the output driving element within a safe range, which in turn prevents overstress and damage to the element.

Abstract: A vertex accumulation buffer for improved three-dimensional graphical processing is disclosed. The accumulation buffer may include two individual buffers (buffers A and B) that each comprise a plurality of individual storage locations that are each configured to store vertex parameter values such as XYZ values, normal values, color information, and alpha information. The individual buffers serve to double buffer the vertex parameter values stored in the accumulation buffer. The storage locations may be written to on an individual basis without overwriting the other storage locations in the buffer.

Abstract: Apparatus, methods and computer program products are disclosed that enable a compiler to generate efficient code to access stack registers on a register stack. The invention operates by transforming a three-operand instruction, within a compiler's intermediate representation, to one or more fewer-than-three-operand instructions. The invention also transforms the instruction's operand addressing from an access to a pseudo-named register to an access to a stack register through stack offset into a register stack. The invention also determines the register stack state at each instruction responsive to register stack permutations and maps the stack offset accordingly for each subsequent access to a stack register.

Abstract: A mechanism in a microprocessor to transform signed data to an unsigned format so that the signed data can be processed by unsigned instructions. In particular, a subtraction of two signed numbers can be transformed into a subtraction of two unsigned numbers.

Abstract: A microprocessor operable to transform unsigned data to a signed format so that the unsigned data can be processed by signed instructions. In particular, a subtraction between two unsigned numbers can be transformed into a subtraction between two signed numbers.

Abstract: In a control block design methodology, a control block is designed, synthesized, and laid out. The control block includes one or more storage devices, such as flops. The flops include a header which buffers signals common to the flops and a storage cell for storing data. A flop grouping tool is used to merge flops having the same type of header into a flop having storage equivalent to the merged flops but using a single header. Multiple instances of the header may be deleted from the control block.

Abstract: A method and apparatus for generating code using parameterized classes which is compatible with an existing class library that was previously generated using unparameterized classes is disclosed. According to the method, parameterized source code is received that contains variables that belong to a plurality of types which are defined by supplying parameter values to a parameterized class definition. Static type checking is performed on the parameterized source code to determine if any incompatible type assignments exist between variables that belong to the plurality of types and values assigned to the variables. If no incompatible type assignments exist, then a homogeneous translation is performed on the parameterized source code to generate unparameterized class code. The unparameterized class code is then compiled to produce code that is compatible with the existing class library that was generated using unparameterized classes.

Abstract: A history mechanism is provided in which user data, which represents signals generated by a user, are stored for subsequent recall and regeneration in a history database in one of two or more categories associated with two or more respective component symbols of the user data. For example, in one embodiment, user data includes alphabetic symbols and a respective category is formed for each letter of the alphabet. User data is parsed into components and stored in the history database in each category corresponding to the initial letter of each component of the user data since the initial letter of each component of the user data is prominent. The user recalls and regenerates the user data by selecting a category corresponding to a letter of the alphabet which is the initial letter of any component of the user data. The user then selects the previously generated user data from a list of previously generated user data classified under the selected category.

Abstract: A non-blocking multiple-phase clocking system for use with domino-type dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a several cascaded dynamic logic gates. The circuit also includes a first flip-flop that is coupled to provide input signal(s) to the first dynamic logic gate of the cascade and a second flip-flop that is coupled to receive output signal(s) from the last dynamic logic gate of the cascade. The clocking system provides a first clock phase to the first dynamic logic gate, a second clock phase to the second dynamic logic gate and so on. A timing analysis is performed of each logic path in the circuit to determine the arrival time of each critical input signals to each dynamic logic gate. The delay between adjacent clock phase is then predetermined so that each dynamic logic gate enters its evaluation phase before the critical input signal(s) to the particular dynamic logic gate arrives.

Abstract: A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing pipeline of the microprocessor in a fashion similar to the instruction which caused the miss (the "miss instruction"). The help instructions use the source operands of the miss instruction to form the miss address, thereby providing the fill address using the same elements which are used to calculate cache access addresses. In one embodiment, a fill help instruction and a bypass help instruction are generated. The fill help instruction provides the input address to the data cache during the clock cycle in which the fill data arrives. The appropriate row of the data cache is thereby selected for storing the fill data. The bypass help instruction is dispatched to arrive in a second pipeline stage different from the stage occupied by the fill help instruction.

Abstract: A microprocessor includes an on-chip low phase noise CMOS LC capacitance oscillator. The LC oscillator is relatively insensitive to power supply fluctuations. In addition, the LC oscillator is operable over a range of frequencies sufficient to support both normal full power operation, and reduced power operation of the microprocessor. The LC oscillator minimizes clock jitter problems and so permits extension of the microprocessor operating frequency to even higher levels than heretofore were possible. An output signal from a phase-frequency detector is a frequency control signal on a frequency control input line of a level converter and filter circuit of the LC oscillator. The output signal from level converter and filter circuit is a filtered frequency control signal on a control voltage input line to a continuously modifiable gigahertz frequency voltage controlled oscillator (VCO) circuit.

Abstract: A method and apparatus for providing trunking support in a network device is provided. According to one aspect of the present invention, a network device includes at least one port that is configured to be included in a trunk. The network device also includes a memory for storing a forwarding database. The forwarding database includes entries containing therein forwarding information for a subset of network addresses. The network device further includes a learning circuit. The learning circuit is coupled to the trunked port and the memory. The learning circuit is configured to modify the forwarding database to reflect an association between the trunked port and a first address contained within a packet received by the trunked port. If the trunk is of a first type, the learning circuit updates the forwarding database based upon a trunk designator corresponding to the trunk; otherwise, the learning circuit updates the forwarding database based upon a port designator corresponding to the trunked port.

Abstract: A system for using a lease to detect a failure and to perform failure recovery is provided. In using this system, a client requests a lease from a server to utilize a resource managed by the server for a period of time. Responsive to the request, the server grants the lease, and the client continually requests renewal of the lease. If the client fails to renew the lease, the server detects that an error has occurred to the client. Similarly, if the server fails to respond to a renew request, the client detects that an error has occurred to the server. As part of the lease establishment, the client and server exchange failure-recovery routines that each invokes if the other experiences a failure.

Abstract: In a distributed object system, a stable object iterator provides a list of all persistent objects within a collection of objects. A plurality of iterators are supported in another aspect of the invention. An iterator associates a label with each persistent object in a collection of stable objects. The label indicates whether the associated object was added to or deleted from the collection before or after the inception of an iterator. Multiple persistent iterators are supported by providing an indication of which iterators each persistent object is, or is not, "visible" to. Should an element of the persistent object collection be created after one or more iterators is created, that element is "invisible" to those iterators. Objects that exist when one or more iterators are created remain "visible" to those iterators, even if the object is deleted from the collection while those iterators still exist.

Abstract: A lighting unit for improved processing of multiple light sources. The lighting unit includes an input buffer for receiving one or more attributes corresponding to a given polygon. The lighting unit further includes a first light parameter storage location for storing a first set of light parameters for a first light source illuminating the given polygon, and a second light parameter storage location for storing a second set of light parameters for a second light source illuminating the given polygon. Still further, the lighting unit includes a first light type storage location which stores a lighting routine index for the first light source, and a second light type storage location which stores a lighting routine index for the second light source. The first light type storage location is initialized to be a current light type storage location. The lighting routine indices point to a particular lighting routine to be performed for a given type of light source.

Abstract: An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and a minimum array size boundary value. The array boundary checking apparatus of the invention includes an associative memory element that stores and retrieves a plurality of array bound values. Each one of the plurality of array bound values is associated with one of the plurality of array access instructions. An input section simultaneously compares the array access instruction identifier with at least a portion of each of the stored array reference entries, wherein the array access instruction identifier identifies an array access instruction. An output section is configured to provide as an array bounds output values one of the plurality of array bound values stored in one of the plurality of memory locations of the associated memory element.

Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: A multi-layer distributed network element for relaying packets according to known routing protocols. A distributed architecture of multiple subsystems delivers routing at wire-speed performance across subnetworks. Each subsystem includes a forwarding memory and an associated memory and is configured to identify unicast and multicast packets for routing purposes, modify the packets in hardware, including replace VLAN information, and forward the packets to the next hop. The routing decisions are made in the inbound subsystem, and packets and associated control information are forwarded, if necessary given the network topology, through a separate outbound subsystem. When packets traverse the internal links from one subsystem to another, encapsulation operations are conducted such as appending an additional cyclic redundancy code (CRC) to the packet before going through the internal link.

Abstract: A rapid method for calculating a local eye vector in a fixed point lighting unit. For a given triangle primitive which is to be projected into a given viewport in screen space coordinates, the local eye vector corresponds to a given eye position and a first vertex of the given triangle primitive. (A different local eye vector is calculated for each vertex of the given triangle primitive). The method first comprises generating a view vector matrix which corresponds to the given eye position and corner coordinates of the given viewport, where the corner coordinates are expressed in screen space coordinates. The view vector matrix is usable to map screen space coordinates to an eye vector space which corresponds to the given viewport. The method next includes receiving a first set of coordinates (in screen space) which correspond to the first vertex. The first set of coordinates are then scaled to a numeric range which is representable by the fixed point lighting unit.