Abstract: An intuitive graphical user interface is based upon a geographic map structure, and includes a system for controlling remote external electronic devices. In the defined graphical user interface, each space of the geographic map structure is rendered on a touch screen display as a graphic image of a geographic space. Within each space are colored cartoon-like icons called "objects" which can be selected and manipulated by the user. Certain objects, referred to as portals, transport the user from one space to another space when Selected. Other objects, referred to as buttons, perform associated actions or functions when Selected. The graphical user interface is displayed on a hand-held display device used to control remote devices. Each remote electronic device transmits a user interface program object that defines a graphical user interface to the display device.

Abstract: Apparatus, methods, and computer program products are disclosed that improve the performance of multi-threaded computer applications that use objects (within an object collection) which require exclusive thread access. The invention monitors interrelationships between the objects in the object collection and provides mechanisms to lock the minimal set of these objects for the exclusive thread access. When these objects are locked, independent or unrelated objects are left unlocked and can, in turn, be locked by other threads. Because a minimal set of objects are locked other threads that access the object collection are less likely to be blocked by the lock. Thus, these other threads are more likely to be able to simultaneously access objects in the object collection.

Abstract: A fault tolerant computer system includes a number of lockstep subsystems, each of which comprises a parallel input signature generator, used for data compression to allow practical comparison of the operation of internal modules of the lockstep subsystem, and a logic analyzer which stores the outputs of the internal modules of the lockstep subsystem. A signature comparator is connected to receive the signatures from the signature generators of the individual lockstep subsystems. The signature comparator generates a trigger signal for triggering the logic analyzers on detecting a difference in the signatures. The logic analyzers store enough states to include the first difference from a module following a detected difference in the signature outputs. The logic analyzer traces are searched automatically after an out-of-sync event to locate the first difference in operation and to determine which internal module provided the faulty output and then that module is labelled as broken.

Abstract: A central processing unit (CPU) of a computer includes a novel prefetch cache configured in parallel with a conventional data cache. If a data cache miss occurs, the requested data is fetched from external memory and loaded into the data cache and into the prefetch cache. Thereafter, if a prefetch cache hit occurs, a prefetch address is derived, and data corresponding to the prefetch address is prefetched into the prefetch cache. This prefetching operation frequently results in the prefetch cache storing data that is requested by subsequently executed instructions in a computer program, thereby eliminating latencies associated with external memory. A software compiler of the computer ensures the validity of data stored in the prefetch cache. The software compiler alerts the prefetch cache that data stored within the prefetch cache is to be rewritten and, in response thereto, the prefetch cache invalidates the data.

Abstract: An apparatus for cooling an electrical component is disclosed which comprises a sorber containing a sorbent; a condenser in fluid communication with the sorber; an evaporator in fluid communication with both the sorber and the condenser and connected in heat-exchange relation to the electrical component; wherein a sorbate which has been condensed in the condenser is evaporated in the evaporator, thereby absorbing heat from the electrical component, and then adsorbed onto the sorbent; an electromagnetic wave generator, a waveguide coupler for directing the electromagnetic waves to the sorbent; wherein the sorbate is desorbed from the sorbent by the electromagnetic waves and condensed in the condenser; and wherein the desorption of the sorbate from the sorbent is substantially isothermal.

Abstract: A graphic screen including data in a table format is displayed in a window. The window implements a Zoom-In function using a Zoom-In display element. A user "Zooms-In" to any row in the table by selecting a row and activating the Zoom-In display element. While displaying the same window, activation of the Zoom-In display element hides the table and displays detailed information in a form format for updating the selected row of the table. The table is hidden and the form format is presented until the user activates a "Zoom-Out" display element, terminating the detailed information form format display and leaving the table display exposed. In the form format, the user performs functions including modifying data relating to a table entry, saving the modified or entered data, proceeding to the next row item, or regressing to the previous row.

Abstract: An interconnect structure includes in a first layer a clock line and a ground line running substantially parallel to the clock line, and a plurality of conductive regions lying in a second layer parallel to the first layer. The ground line is coupled to a source of ground potential. The conductive regions are aligned with the clock line and are disposed around a signal line routed in the second layer across the clock line. The conductive regions are electrically connected to the ground line, thereby forming a shield for the clock line that helps prevent clock signals propagated on the clock line from electromagnetically coupling with other signal lines. In one embodiment, a clock distribution network includes conductive regions (501, 503, 505. . . ) in the metal layer below the clock line layer and two parallel ground lines (201, 203) in the same metal layer as the clock line (101). The conductive regions (501, 503, 505 . . .

Abstract: Methods and apparatus for dynamically determining whether portions of code should be interpreted or compiled in order to optimize a software application during run-time are disclosed. According to one aspect of the present invention, computer-implemented method for run-time processing of a computer program which includes byte-codes arranged as a plurality of methods includes invoking a first method selected from the plurality of methods. Invoking the first selected method involves interpreting the first selected method. An invocation tracker which is arranged to track the number of invocations of the first selected method is updated, and a determination is made regarding when the invocation tracker indicates that the number of invocations of the first selected method exceeds a threshold value. The first selected method is compiled when it is determined that the invocation tracker indicates that the number of invocations of the first selected method exceeds a threshold value.

Abstract: An improved method for routing interconnect lines in a VLSI chip using repeaters. First, an optimal virtual assignment of the repeater locations is determined according to a suitable method. The "virtual" assignment is the ideal location irrespective of where logic blocks which could form a repeater cell might located. Next, repeaters are assigned to physical locations close to the optimal virtual locations. Finally, an optimal global routing is done using the physical locations of the repeaters. The optimal global routing revises the original global routing upon which the original optimal virtual assignment of repeaters was done. Preferably, blocks of circuitry and routing channels are identified first. Instead of simply routing the interconnect lines through the channels, a portion of the interconnect lines are routed through available spaces in the blocks themselves. This will reduce the number of turns required both through the channels and to reach a repeater.

Abstract: A method and system for managing control information associated with a file is disclosed. According to the method, a cache is established in a first file block for storing a second type of file control data. The cache has a cache range. In response to receiving a command to write the file, a first and second type of file control data is generated. The second type of file control data has a logical block number identifying a location in the second file block where the second type of file control data is to be stored. The first type of file control data is stored in the first file block. If the logical block number is within the cache range, then the second type of file control data is stored in the cache. If the logical block number is outside the cache range, then the cache is flushed by copying the previously stored second type of file control data in the cache to a second file block. The second type of file control data is then written into the cache.

Abstract: An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized graphics instructions and accompanying hardware for executing them are disclosed to optimize the execution of graphics instruction with minimal additional hardware for a general purpose CPU.

Abstract: In the system of the present invention, a time critical program operating in a window system environment is implemented. The application program containing time critical procedures is divided functionally into two or more processes. The first process contains all of the CPU time slice sensitive or time critical procedures. This process operates independently of the window system interface and communicates directly with the operating system. The second process implements all procedures which require the user input and output through the window system but not including time critical procedures. This process communicates with and operates through the window system interface. The processes exchange data and synchronize execution through the interprocess communication mechanisms such as shared memory such that the two or more processes operate and appear as a single process to the user while insulating the first process from suspension due to window system operations and blocking procedures.

Abstract: A logical address and a pointer entry for a file in an indirect address file system are translated into a physical address. A decision module tests a pointer flag in a present pointer entry. The pointer entry has a pointer and a pointer flag to identify whether the pointer points to a data storage area or a metadata storage area. The decision module indicates whether the pointer is a data pointer or a metadata pointer. In response to the decision module indicating the pointer is a data pointer, a set module combines the data pointer with the logical address to generate a physical address. A split module, in response to the decision module indicating the pointer is a metadata pointer, divides the logical address into a first portion as an index value and a remaining portion as an offset value. An update module then sets the logical address to the offset value. A retrieve module combines the metadata pointer with the index value to get the next pointer entry.

Abstract: Improved word accuracy of speech recognition can be achieved by providing a scheme for automatically limiting the acceptable word sequences. Speech recognition systems consistent with the present invention include a lexicon database with words and associated lexical properties. The systems receive exemplary clauses containing permissible word combinations for speech recognition, and identify additional lexical properties for selected words in the lexicon database corresponding to words in the received exemplary clauses using lexical property tests of a grammar database. Certain lexical property tests are switchable to a disabled state. To identify the additional lexical properties, the exemplary clauses are parsed with the switchable lexical property tests disabled to produce an index of the lexical properties corresponding to the exemplary clauses.

Abstract: A circuit used to control the modification of content within memory implemented within an address translation unit. This memory includes a plurality of entries which contain virtual and physical addresses associated with an address translation. The circuit includes an update control circuit coupled to the address translation circuit. The update circuit is configured to set an entry to an invalid state or point to an entry to be loaded with a new address translation. The circuit further includes a flush control circuit that is configured to control the update control circuit. Such control includes setting an entry to an invalid state upon detecting a particular event.

Abstract: Data structures and various methods for invoking and creating objects are used in a distributed object system in order to implement subcontracts. A subcontract is a selected grouping of basic features or object mechanisms that a system provides for use in managing objects and has associated functions. A subcontract registry is used for creating object references for server objects. The subcontract registry has any number of subcontract objects within it, and each subcontract object may include: a subcontract identifier that identifies the subcontract object, a quality of service list that contains feature name-value pairs, and a create function unique to the subcontract object. An implementation registry is used for registering any number of implementation definitions.

Abstract: An application binary interface includes linkage structures for interfacing a binary application program to a digital computer. A function in a relocatable shared object module obtains the absolute address of a Global Offset Table (GOT) in the module using relative branch and link instructions through the computer's link register. A dynamic linker lazily constructs a Procedure Linkage Table (PLT) and a pointer table for an object module in a process memory image in which space is allocated for the PLT, but the PLT is not initially provided. The pointer table stores absolute addresses of external functions that cannot be reached by relative branching from the module. The PLT receives calls to these functions, gets the absolute addresses from the pointer table and branches to the absolute addresses of the functions. The PLT also receives calls to functions that can be reached by relative branching from the module, and causes relative branching to the functions.

Abstract: A method for creating a table object made up of one or more columns, where the table object can be used as a programming interface or wrapper for an underlying table component is described. The table is made up of one or more column objects that can be used in other tables with minor alterations. The column objects are created to hold data of one type. This type can be a basic data type or a specialized graphical user interface type, allowing for great flexibility in creating table data structures for holding data of a wide variety. The table object is used to facilitate the use of an underlying table component, which may contain its own search engine. The table object acts as a wrapper for the table component allowing the application developer to use columns from other tables for use with a particular underlying table component without having to recreate or rewrite computer code for that particular underlying table component.

Abstract: Apparatus, methods, systems and computer program products are disclosed that provide enhancements to client-side image maps in HTML based documents. These enhancements provide audio feedback to a user of a HTML capable application as to the hyperlinks associated with an area in an image. These enhancements also provide a visual representation of the areas defined by a client-side image map when the image is not available.

Abstract: A bus line is provided with broadly distributed signal termination by using switched termination logic where the pull up resistance of a driver corresponds to the characteristic impedance of the line and the pull down resistance of the driver corresponds to the number of drivers coupled to the line. Accordingly, signals being transmitted over the bus suffer relatively few reflections thus advantageously producing a shortened signal settling time, thereby increasing the attainable signaling frequency.