Abstract: A computer system architecture is described for providing increased performance in a counterflow pipeline processor. The system includes an instruction fetching unit, a register file, and a pipeline connected between the instruction fetching unit and the register file. The pipeline is formed from a group of sequential stages. Each stage in the pipeline includes a first instruction register for storing a first instruction, a second instruction register for storing a second instruction, and a first results register for storing results. The instructions are transferred in a first direction from stage to stage, and results are transferred in an opposite direction from stage to stage. The registers for the instructions include an operand field, a first source field for the operand, a second source field for the operand, and a destination field. Each of the fields itself includes a register name, a value, and a validity bit.

Abstract: The present invention provides for a method and apparatus for reading non-cachable information in a cache memory system. The cache memory system includes a processor, a buffer, a multiplexor, main memory, an input/output unit, a cache controller, a memory management unit, and cache memory. In a read operation, the processor directs a read operation specifying a first address to the cache memory. The cache controller initially determines whether the information desired is cachable or non-cachable. If the information desired is determined to be non-cachable, the cache controller causes any information presently contained in a first location in the cache memory to be stored in the buffer. In the interim, the cache controller causes the memory management unit to initiate an access of the information desired from the first address. Once accessed, this information is temporarily written into the first location within the cache memory.

Abstract: Several designs of a stage for use in a FIFO pipeline are disclosed. Each stage includes a latch that is capable of latching a data element and capable of transitioning between a transparent state and an opaque state. The stages also include a control circuit capable of announcing the availability of the data element to the next stage as soon as the data element has propagated through the latch and without any latching or unlatching action of the latch prior to the announcement of the availability of the data element. In other words, if the latch of a stage is transparent and receives a signal Ri from the previous stage, the control circuit of the stage generates signal Ro after receiving signal Ri, thus enabling the next stage to latch the data element before the current stage has itself latched that data element.

Abstract: A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.

Abstract: A method includes operating a general purpose computer system to minimize signal-propagation delay time of a long line of a simulated circuit. A design engineer empirically derives two rule bases, the first of which determines whether to divide the long line into two or more segments by inserting repeater amplifiers into a long line to minimize the propagation delay through the line. The second rule base relates optimum amplifier size for driving long lines to line length. These rule bases are stored in a main memory of the computer system. The computer system is configured to apply the first rule base to the long line to determine whether to divide the long line into two or more segments by inserting repeater amplifiers, and to apply the second rule base to optimize the size of each of the repeater amplifiers. The resulting long line, segmented by size-optimized repeater amplifiers, provides minimal signal-propagation delay.

Abstract: Disclosed are a die carrier and associated method for conducting probe beam tests on chips designed to be packaged in flip-chip packages. The die carrier is a specially modified membrane type carrier that includes a probe access region, such as an opening, in the membrane. A die to be tested is mounted in the die carrier such that its I/O pads make electrical contact with corresponding bump contacts on the membrane. The die/carrier assembly is then mounted in a test socket provided on a chip testing apparatus such that electrical I/O signals can be provided to and from an external test circuit. While the die is being electrical tested, a probe beam is directed through the probe access region and onto the chip active surface. In this manner, the chip active surface is probed while exposed to electrical stimulus.

Abstract: Disclosed is an instruction-level method and system for prefetching data or instructions of variable size to specified cache sets. A prefetch instruction containing binary fields allows the compiler, loader or runtime software to control cache prefetching and reduce thrashing by providing the prefetch hardware with information as to the optimal cache set location and the optimal amount of data to be prefetched. Support of Harvard architectures with separate instruction and data caches is provided by separate software control of instruction and data caches. The cache set number is identified to indicate into which set the information is to be preloaded. The size field provides a variable prefetch size. An address field indicates the address where prefetching begins.

Abstract: A method implemented on a computer system for loading a module for input and for loading a module for output for an application program includes the steps of selecting the module for input, loading the module for input, selecting a module for output, and loading the module for output at a time different from the loading of the module for input.

Abstract: Disclosed herein are methods and apparatus for discovering devices on a network. Active devices can be discovered in ARP tables from routers on the network. Pings can then be sent to the active devices for verification, or pings can be sent to devices at other addresses on the network. Devices can also be discovered by sending a batch of pings to addresses on the network and monitoring responses from those addresses over an interval. After the interval elapses, another batch of pings can be sent. The devices can be discovered by a host on the network or by a network manager. The network manager can add the discovered devices to a network topology database.

Abstract: Methods, apparatti and computer program products allow one or more editors to provide integrated functionality with one or more applications. The methods, systems and computer program products allow a user to select from among several editors which are not integrated with an application, yet interact with the editor and application as though the editor and application were integrated. One or more editors are assigned to each application and commands sent from each application are transformed into a command readable by the editor associated with the application. The command is sent to the editor, which is then able to display files to provide an appearance that the editor and the application are integrated. User generated commands from the editors may be sent to all of the applications or only a subset of the applications to allow the user to control one or more applications from the editor user interface.

Abstract: A method, in a computer system having a first plurality of stored data objects and capable of running multiple threads concurrently, for preventing access conflicts. The method includes the step of providing a dynamic lock structure having a plurality of dynamic lock structure members. There is also the step of mapping a second plurality of stored data objects of the first plurality of stored data objects into a first dynamic lock structure member of the plurality of dynamic lock structure members in accordance with a mapping function. Due to the mapping function, the plurality of dynamic lock structure members become fewer in number than the number of the first plurality of stored data objects. The first dynamic lock structure member is configured to store identities of a third plurality of stored data objects.

Abstract: A central processing unit (CPU) of a computer and a method for reducing memory latencies in a computer memory hierarchy are described. The CPU includes an external cache controller and a primary memory controller. An instruction buffer in the primary memory controller stores an address from a primary memory page corresponding to a previous address request. A comparator circuit of the primary memory controller is used to compare a present address request corresponding to an instruction cache miss signal to the address stored in the instruction buffer. If an instruction buffer hit is achieved, memory latencies associated with the external cache controller and the primary memory controller are avoided. If an instruction buffer miss is experienced, the primary memory controller, under predetermined conditions, stores, in the instruction buffer, an address following an address corresponding to data from a primary memory page specified by the present address request.

Abstract: A method, apparatus, and software for efficiently allocating discontiguous stack space without requiring compiler changes are described. In one aspect, a method is provided for executing a compiled function that is located in a first computer memory stack chunk such that additional memory is allocated efficiently if a determination is made that such additional memory is necessary for execution of the compiled function. In one embodiment, the method includes calling a stack checking function that includes the compiled function. A determination is made if additional memory is required for executing the compiled function. If no additional memory is required, then the compiled function is called and executed. However, if additional memory is necessary, then additional memory is allocated that is discontiguous with the original memory stack.

Abstract: A message management system produces files necessary for generating messages, localizing message catalogs, and displaying online help messages from a single master message file. Revisions and up-dates of the message system are performed by editing a single file, the master message file. A set of tools is provided to process the master message file to build the outputs.

Abstract: A land grid array package or a ball grid array package is electrically connected by an elastomeric type layer (containing alternating elements of conductive and non-conductive silicone) to a printed wire board or motherboard. A hold-down collar engages the peripheral edges of the package and snaps into holes in the board in such manner as to create pressure on the elastomeric layer, causing the layer to compress and create through-going electrical paths between exposed lands or conductive elements on the bottom of the package and exposed conductive elements on the wiring board. In one embodiment, solder balls adhere to the exposed conductive elements on the bottom of the package. In this embodiment the collar is initially in two pieces which are fitted together to engage both the top and bottom edges of the substrate.

Abstract: Apparatus and methods are disclosed for scheduling target program instructions during the code optimization pass of an optimizing compiler. Most modern microprocessors have the ability to issue multiple instructions in one clock cycle and/or possess multiple pipelined functional units. They also have the ability to add two values to form the address within memory load and store instructions. In such microprocessors this invention can, where applicable, accelerate the execution of modulo-scheduled loops. The invention consists of a technique to achieve this speed up by systematically reducing the number of certain overhead instructions in modulo scheduled loops. The technique involves identifying reducible overhead instructions, scheduling the balance of the instructions with normal modulo scheduling procedures and then judiciously inserting no more than three copies of the reducible instructions into the schedule.

Abstract: An application binary interface includes linkage structures for interfacing a binary application program to a digital computer. A function in a relocatable shared object module obtains the absolute address of a Global Offset Table (GOT) in the module using relative branch and link instructions through the computer's link register. A dynamic linker lazily constructs a Procedure Linkage Table (PLT) and a pointer table for an object module in a process memory image in which space is allocated for the PLT, but the PLT is not initially provided. The pointer table stores absolute addresses of external functions that cannot be reached by relative branching from the module. The PLT receives calls to these functions, gets the absolute addresses from the pointer table and branches to the absolute addresses of the functions. The PLT also receives calls to functions that can be reached by relative branching from the module, and causes relative branching to the functions.

Abstract: A method and apparatus for controlling access to services within a computer network is provided. More specifically, the present invention includes a services management system, or SMS. The SMS manages network connections between a series of client systems and a router. An access network control server (ANCS) manages the configuration of the router. For each network user, the SMS maintains a profile of filtering rules. When the user accesses the network, the SMS downloads the user's filtering profiles to the ANCS. The ANCS then uses the downloaded filtering profiles to reconfigure the router. The router then uses the filtering rules to selectively forward IP packets originating from the user's host system and directed at the network services.

Abstract: An eyetracker is used to control power to an electrical device such as a computer display screen so that power consumption is reduced when a user's eyes and therefore a user's attention are not directed to the device. A motion detector activates a proximity detector and/or an IR detector to ensure that power is applied only when a user is actually present.

Abstract: An automated method and system for detecting electromigration violations in signal lines of an integrated circuit design to be fabricated is disclosed. The automated method and system checks conductive traces, vias and/or contacts that are used to route signals to and from various functional cells within the integrated circuit design against predetermined process rules to detect electromigration violations. The operation and effectiveness of the automated method and system are far superior to conventional manual approaches.