Abstract: A computer instruction execution unit includes different execution paths for different categories of instructions. Different execution paths share circuitry. The slower execution paths are pipelined. In some embodiments, all execution paths are pipelined. Fast instructions are executed by a fast execution path. Slower instructions are executed by a slower execution path. Faster instructions immediately following the slower instruction are also executed by the slower execution path not to block the shared circuitry. Consequently, the throughput is increased and the average instruction execution latency is reduced. When a sufficient number of clock cycles occur with no instructions started, subsequent fast instructions are executed by the fast execution path.

Abstract: A multilevel port system on a computer operating under a multilevel operating system to permit contemporaneously opening a plurality of sockets having the same port number while meeting the requirements of an appropriate security policy, thus allowing third party applications to run as if they were unimpeded by the security policy, and methods thereby. The computer system having an operating system adhering to an access control security mechanism. Such systems include government systems wherein a hierarchy of security classification levels are defined (e.g., top secret, secret, classified, unclassified), and commercial systems. Sensitivity labels pursuant to an access control security mechanism include at least hierarchical security classifications, and may include non-hierarchical categories or compartments which represent distinct areas of information in a system.

Abstract: Certain bits in existing op code formats for a processor do not change from one instruction to another when particular classes of instructions are used. Applicants optionally utilize one or more of these bits to identify one of a plurality of different register files from which to retrieve operands or to store the results of an operation. These bits along with allocated address bits in predetermined address fields now allow the processor to address many more registers. This can be used to increase the performance of the processor. Those programs not utilizing the bits outside of the address fields for designating a particular register file are backwards compatible with the modified processor.

Abstract: Methods and apparati including computer program products link compiler error messages to information relevant to an error causing the compiler to generate the error message by adding link information to the compiler error messages. The error messages are displayed to the user without the link information. Portions of the visible error messages pertaining to the link information are highlighted, and upon selection by the user of the highlighted portion of the error message, information relevant to the highlighted error message is automatically displayed, for example, by running an editor, loading the source file which generated the error message, and displaying the relevant portion of the source file, or by running a help facility and displaying help information relevant to the error.

Abstract: A refrigeration system capable of providing cooling during at least a portion of a repeatable refrigeration cycle, the refrigeration system comprising at least one sorber having a housing forming an enclosure, a sorbent located within the enclosure, an evaporator in fluid communication with the enclosure, a condenser in fluid communication with both the enclosure and the evaporator, wherein a sorbate is evaporated in the evaporator to provide a cooling effect and then adsorbed by the sorbent, an electromagnetic wave generator, a waveguide coupler for coupling electromagnetic waves generated by the generating means to the sorber, wherein during a desorb portion of the refrigeration cycle the sorbate is desorbed from the sorbent by the electromagnetic waves and then condensed in the condenser, wherein the desorption of the sorbate from the sorbent is primarily isothermal, and a controller for controlling the operation of the generator, wherein the generator is selectively activated and deactivated to initiate a

Abstract: Hardware and software improvements in workstations which utilize virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes. In virtual addressing, multi-user workstations, system performance may be improved significantly by including a virtual address write back cache as one of the system elements. Data protection and the reassignment of virtual addresses are supported within such a system as well. Multiple active processes, each with its own virtual address space, and an operating system shared by those processes in a manner which is invisible to user programs. Cache "Flush" logic is used to remove selected blocks from the virtual cache when virtual addresses are to be reassigned.

Abstract: Architectural support is provided for trapping of garbage collection page boundary crossing pointer stores. Identification of pointer stores as boundary crossing is performed by a store barrier responsive to a garbage collection page mask that is programmably encoded to define a garbage collection page size. The write barrier and garbage collection page mask provide a programmably-flexible definition of garbage collection page size and therefore of boundary crossing pointer stores to be trapped, affording a garbage collector implementer with support for a wide variety of generational garbage collection methods, including train algorithm type methods to managing mature portions of a generationally collected memory space. Pointer specific store instruction replacement allows implementations that provide an exact barrier not only to pointer stores, but more particularly to pointer stores crossing programmably defined garbage collection page boundaries.

Abstract: A database management system incorporating an intermediate level of storage medium. Software of the DBMS controls the transfer of data between a primary, secondary and intermediate storage mediums. This transfer is under control of the DBMS and is not transparent to the DBMS. The intermediate storage medium has an access time that is shorter than the access time of the secondary storage medium. During operation of the DBMS, data is read from the secondary storage medium and held in the primary storage medium until the storage medium is full. Thereafter, as additional data is read by the DBMS from the database stored on the secondary storage medium, data is transferred to the intermediate storage medium under control of the DBMS, thus preserving the benefit of having the data read into the primary storage medium.

Abstract: A method and apparatus for allowing a user to select one of a plurality of mutually-exclusive options. A set of visual objects are displayed on the display device of a computer system. Each of the visual objects in the set corresponds to one of the mutually-exclusive options. No more than one of the visual objects is displayed in a selected state. The remainder of the visual objects in the set are displayed in an unselected state. The user selects one of the mutually exclusive options by performing a first action that selects one of the visual objects in the set, and then a second action that selects the option associated with the selected visual object. When the user performs the first action, the selected visual object is displayed in an excited state, and the remainder of the visual objects are displayed in a disappointed state.

Abstract: A method for dynamically adding new functionality to a first set of instructions that processes Web documents. The invention includes the first step of the first set of instructions decoding a first statement of the Web document. The first statement includes a first command and at least one instruction provided as an argument to the first command. In response to executing the first command, the first set of instructions decodes the instruction provided as the argument to the first command and issues the instruction to be executed. Executing the instruction provided as an argument to the first command, results in new Web document processing functionality being added to the first set of instructions.

Abstract: The present invention is a method, apparatus and computer program product for discovering the nodes and other network information of a computer network (the target network) from a device or node that is not part of the target network (the discovery node) when the discovery node uses a different network protocol than the target network. The invention involves identifying one or more additional nodes (the target nodes) that have access to network information about the target network and with whom the discovery node can communicate. This target network information can include the identification of nodes which are present on the network, the topology of the network, the services provided by the network or by the nodes on the network, status information as the network changes such as information about network and node events or alarms, etc.

Abstract: A structural foam, injection molded superstructure is attached to a motherboard by means of threaded inserts. The superstructure is formed with guide ways for CPU processor modules, and also for the edges of PCI cards. Features of the structure include cam levers on the CPU modules to install and extract the modules. A metal transverse vertical retaining bracket is attached to the superstructure to hold sides thereof parallel and prevent splaying of the free, open end of the superstructure upon extraction of CPU processor modules. The assembly provides stiffness to the motherboard.

Abstract: The present invention teaches a variety of methods and apparatus. The steps of one method for wiring an electrical system having a first bus and a second bus are as follows. Routing a wire B between wires A and A' and a wire B' adjacent to wire A' within the first bus, the wire B intended to transmit a first signal, the wire B' intended to transmit a signal associated with the first signal, the wire A intended to transmit a second signal, and the wire A' intended to transmit a third signal associated with the second signal. Routing a wire D between wires C and C' and a wire D' adjacent to the wire C' within the second bus, the wire D intended to transmit a fourth signal, the wire D' intended to transmit a signal associated with the fourth signal, the wire C intended to transmit a fifth signal, and the wire C' intended to transmit a sixth signal associated with the fifth signal.

Abstract: A dynamic signal appearing across the output of a logic circuit is converted into a static signal using a dynamic-to-static conversion method which minimizes glitching in the static output. A pull-down device, operatively coupled between an output node and a ground, which is closed while an input node is at a precharge potential and is open while the input node is at a ground potential, and a pull-up device, operatively coupled between a source voltage and the output node, is closed while the input node is at the ground potential and is open while the input node is at the precharge potential.

Abstract: A non-fault-only (NFO) bit is included in the translation table entry for each page. If the NFO bit is set, non-faulting loads accessing the page will cause translations to occur. Any other access to the non-fault-only page is an error, and will cause the processor to fault. A non-faulting load behaves like a normal load except that it never produces a fault even when applied to a page with the NFO bit set. The NFO bit in a translation table entry marks a page that is mapped for safe access by non-faulting loads, but can still cause a fault by other, normal accesses. The NFO bit indicates which pages are illegal. Selected pages, such as the virtual page 0x0, can be mapped in the translation table. Whenever a null-pointer is dereferenced by a non-faulting load, a translation lookaside buffer (TLB) hit will occur, and zero will be returned immediately without trapping to software to find the requested page.

Abstract: Method, system and article of manufacture for dynamic editing of object oriented components used in an object oriented applet or application. An editor window is defined in predetermined class templates as a method corresponding to the editor. Then, when a component is instantiated from one of said predetermined classes, the editor is automatically opened to permit the user to make changes in the component's properties. When editing is completed, the editor window is closed, the changes are accepted and then displayed for the edited component. Components are thereafter monitored for a user re-editing request which, when detected, causes the editing cycle to be initiated.

Abstract: An interrupt mechanism handles an interrupt transaction between a source processor and a target processor on separate nodes in a multi-processor system. The nodes are connected to a network through node interface controls between the node and the network. The transaction begins by initiating the interrupt transaction at the source processor. The interrupt mechanism detects if the target processor is at a remote node on a system bus across the network, and if it is the mechanism sends an ignore signal to the source processor. Then the mechanism suspends the interrupt transaction at the source processor if it detects the target processor is at a remote node. The mechanism performs an ACK/NACK (acknowledge/non-acknowledge) operation at the target processor and returning an ACK signal or a NACK signal to the source processor across the network. This ACK/NACK signal wakes-up the source processor.

Abstract: Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state machine and an input block, whose outputs are coupled to a barrel shifter unit. Input block output also is input to Huffman tables that output to the state machine. The state machine output also is coupled to a data path controller whose output is coupled to a tag decoder, and to a normal processor receiving output from the barrel shifter unit. The decompressor unit also includes a position/color processor that receives output from the barrel shifter unit. Outputs from the normal processor and position/color processor are multiplexed to a format converter. For instructions in the data stream that generate output to the format converter, the decompression unit generates a tag sent to the tag decoder in parallel with bits for normals that are sent to the format converter.

Abstract: Data elements which can be combined to define a state are defined by respective attributes of an attribute set. An attribute includes an identifier, a data type, an accessor, and procedures for storing and retrieving values of the data element. A context includes at most one value for each attribute of an attribute set. Different contexts can have different respective values for the same attribute. Since an attribute includes a data type and procedures for storing and retrieving values of the attribute, type checking error detection mechanisms of the computer instruction language in which the attributes are implemented remain in effect. In addition, attribute values are stored in an ordered structure, e.g., an ordered list, in each context and the location within the ordered structure at which an attribute value corresponding to a particular attribute is stored in the particular attribute. As a result, attribute values are accessed within contexts in a particularly efficient manner.