Abstract: A polling and communications device permits a speaker to interact with an audience in data or voice modes. Questions can be transmitted to the speaker in data form. Alternatively, the speaker can selectively activate a wireless microphone for a particular member of the audience in response to an indication, sent over a data channel that a user has a question. Alternatively, a user can record a voice message and store it in memory for transmission over a data link. Information about a questioner is provided to the speaker from information stored during registration for the event and may also be provided to the audience.

Abstract: A method for providing a triangularly shaped I/O region on the periphery of an integrated circuit in order to reduce the amount of unused surface area on the integrated circuit is disclosed. A core region within the triangularly shaped I/O region may be either triangularly shaped or rectangularly shaped, and may include one or more metallization lines routed in a direction parallel to at least one edge of the triangularly shaped I/O region on the periphery of the integrated circuit. Alternatively, the core region may include one or more metallization lines routed in a direction parallel to at least one edge of the triangularly shaped peripheral I/O region, as well as one or more other metallization lines routed in a direction perpendicular to at least one edge of the triangularly shaped peripheral I/O region. A plurality of I/O slots located in the triangularly shaped I/O region may be triangularly, trapezoidally, or rectangularly shaped.

Abstract: A method and apparatus for storing associated data in a computing system having two or more storage devices arranged in a RAID configuration. The storage devices have a prewrite area for pre-storage of the data, and data region for persistent storage of the data. A scoreboard memory structure is created for monitoring the state of the prewrite area, and data in the prewrite area is conditionally invalidated based upon the information contained in the scoreboard memory structure. By conditionally invalidating the prewrite data, the write performance of the RAID storage system is improved.

Abstract: A computer system in a distributed object programming environment includes a number of host computers providing services to clients on a network through internally stored servers. Various types of configuration information for each server are available to clients through persistent server administrators, which are objects containing such information about individual servers. A server administrator can store such information as startup execution definitions, saved program definition, object interfaces and implementations, reaping, tracing, and logging configuration data. Being persistent and external to the server, the server administrator can manipulate and determine its information about a server in response to client requests without starting up the server, thereby facilitating system administration.

Abstract: An absorbent pair refrigeration system comprising a source of liquid refrigerant; an evaporator for transforming the liquid refrigerant into vapor refrigerant at a lower temperature than the liquid refrigerant to thereby provide a desired cooling effect; a volume of absorbent in communication with the evaporator, wherein the vapor refrigerant is absorbed onto the absorbent; an electromagnetic wave generator for desorbing the vapor refrigerant from the absorbent without appreciably heating the absorbent; and a condenser in communication with the absorbent for condensing the vapor refrigerant which has been desorbed from the absorbent.

Abstract: A "slow" signal is not sent across chip to be combined with combinatorial logic, but rather, the logic with which it would be combined is partitioned such that there are two outputs, one if the "slow" signal would be true and a second if the "slow" signal would be false. Both of these outputs are then provided to a multiplexer. The original "slow" signal selects the correct signal, thus saving the interconnect time delay. The concepts also apply to combinations of multiple "slow" signals.

Abstract: A partially relocated object identifier store including "copy from" and "copy to" identifier storage accessible to write and read barrier logic allows the write and read barrier logic to selectively direct store- and load-oriented accesses to an appropriate FromSpace or ToSpace instance of a partially relocated memory object, in accordance with the memory object's partial relocation state. In some embodiments, the barriers trap to a partially relocated object trap handler. In other embodiments, the write barrier itself directs accesses without software trap handler overheads. Optional "how far" indication storage facilitates differentiation by the barrier logic, or by the partially relocated object trap handler, between a copied portion and an uncopied portion of the partially relocated memory object.

Abstract: An apparatus for cooling an electrical component is disclosed which comprises a sorber containing a sorbent; a condenser in fluid communication with the sorber; an evaporator in fluid communication with both the sorber and the condenser and connected in heat-exchange relation to the electrical component; wherein a sorbate which has been condensed in the condenser is evaporated in the evaporator, thereby absorbing heat from the electrical component, and then adsorbed onto the sorbent; an electromagnetic wave generator; a waveguide coupler for directing the electromagnetic waves to the sorbent; wherein the sorbate is desorbed from the sorbent by the electromagnetic waves and condensed in the condenser; and wherein the desorption of the sorbate from the sorbent is substantially isothermal.

Abstract: In its various embodiments, the present invention provides a method and apparatus for creating a target executable program from the source code of a target computer program for execution on a target processor. The target processor provided by the method and apparatus has a first set of registers and a second set of registers. Generally, the target processor is capable of executing a first set of instructions which only address the first set of registers. The method and apparatus provides a second set of instruction for the target processor which include a subset of frequently executed instructions within the first set of instructions. These second set of instructions are novel because they able to address both the first set of registers and the second set of registers. A compiler is provided and used for compiling the source code into a number of target executable instructions and allocating the registers on the target processor.

Abstract: An editor for structurally represented computer programs transforms user-entered text on-the-fly into a stream of tokens that constitute words of the program under edit. Each token is classified as one of group of extended lexemes, and based upon token stream information the editor prettyprint displays the program as the user types. Prettyprinting involves typesetting each token in a visually distinct manner and displaying a varying amount of visual inter-token whitespace between the tokens, based upon token lexical type. The program may be user-edited from the prettyprinted display as though the program were internally represented as text. Cursor position and display appearance depend on the lexical types of tokens adjacent the cursor. To improve aesthetics of the prettyprinted display, a user may insert one or more alignment markers into lines of associated text. The presence of such marker(s) forces horizontal alignment between associated text lines containing such markers.

Abstract: When a cursor is placed over a "back" button or a "forward" button, a list of URLs that have been recently visited, is displayed. This enables the user to immediately visualize the information space accessible using the back and forward buttons. Each URL listed is accompanied by a page title or other descriptive information. A user can select one of the URL's on the list and immediately reconnect to that page.

Abstract: A prefetch apparatus optimizes bandwidth in a computer network by prefetch accessing data blocks prior to their demand in an ATM network thereby effectively reducing memory read latency. The method of the preferred embodiment includes the steps of: 1) computing a prefetch address of a next sequential data block given an address of a requested data block; 2) comparing a current request address against a previously computed prefetch address; and 3) generating a hit/miss indication corresponding to whether the current request address matches the previously computed prefetch address.

Abstract: A cache memory array stores two-way set associative data. An odd set data bank stores odd number sets of the two-way set associative data, where the two ways of each odd number set are aligned horizontally within the odd set data bank. An even set data bank stores even number sets of the two-way set associative data, where the two ways of each even number set are aligned horizontally within the even set data bank. Also, the odd set data bank is aligned horizontally with the even set data bank such that each odd number set is aligned horizontally with a next even number set. The horizontally aligned ways are interleaved for data path width reduction. Set and way selection circuits extract lines of data from the array. The array may be structurally implemented by single-ported RAM cells.

Abstract: A method and apparatus for creating and maintaining a computer database using a virtual index system. The database of the present invention is organized as a hierarchical, tree-like structure. At the most basic level, the hierarchy consists of data objects. The intermediate levels of the hierarchy group the data objects into object classes. Each object class is allocated a class descriptor table having one entry for each class member. Each entry is a poly radix bit string which describes the corresponding data object and may be hashed to return a pointer to the data object. The top level of the hierarchy is a global object table containing one entry for each object class. Each entry is a poly radix bit string which contains data which describes a particular object class and may be hashed to return a pointer to the instance table associated with the object class.

Abstract: A method and apparatus for packet-switched flow control of transaction requests that maximizes resource utilization and throughput, and minimizes latency. An interconnect system controller provides dedicated transaction request queues for master interfaces and controls the forwarding of transactions to slave interfaces. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. An acknowledgement from a downstream queue indicates to the sender that there is space in it for another transaction. Accelerated processing of transaction requests from a processor to a slave device on its local address bus is achieved by immediately forwarding the request to the slave device while determining the validity of the request for that slave, including whether the slave's input queue can accept it.

Abstract: A system providing capability security for distributed object systems is disclosed. The basic tenet of capability security is that the right to do something to an object (e.g., invoke a particular object's methods) is represented solely by the holding of a reference to that object. In each of the preferred embodiments described herein, an object is presumed to hold legitimately a reference to a particular object only if the object knows some unpublicized (except under the conditions required by capability security) key associated with the particular object. That is, an object's key is required along with the object's reference. So that capability security is preserved when object references are passed between objects in different processes, the object references being passed are encrypted upon transmission and then decrypted upon arrival at their intended destination.

Abstract: A shroud attachment (10) for positioning a CPU module (14) relative to a cooling fan (12) on a motherboard (18) and within a computer chassis (24). Shroud (10) includes a vented cooling fan enclosure (11), a CPU mounting section (13), a swing clip (60), fastener mounts (63, 65) for holding captive fasteners (20, 22), which secure motherboard (18) to chassis (24) and provide electrical ground points. Side rails (56, 58) capture side edges of CPU module (14), which includes an enclosure housing (16) for directing cooling air flow past the CPU.

Abstract: A computer system includes multiple local buses to which processors and other devices may be connected. A repeater is coupled to each of the local buses. Additionally, a top level repeater is coupled to each of the repeaters. The repeaters transmit transactions from the corresponding local buses to the top repeater. The top repeater, based upon the local or global nature of the transaction, transmits the transaction to one or more of the repeaters. The repeaters receiving the transaction then transmit the transaction upon the local buses attached thereto. If the transaction is a local transaction, the top repeater transmits the transaction to those repeaters which are configured into a local domain with the repeater which detected the initial transaction. The local domain comprises one or more repeaters which are logically interconnected. The local buses attached thereto logically form one SMP bus to which devices may be attached. Alternatively, the transaction may be a global transaction.

Abstract: A dynamically reconfigurable hybrid computer system is provided that executes transaction requests in one of two ways--either as packet-switched transactions or as circuit-switched transactions. Each transaction request is inspected as it is issued by a master device in the system, and it is determined in each case whether the transaction should be executed as a packet-switched transaction or as a circuit-switched transaction. Preferably, all slave read requests in a uniprocessor system are executed as circuit-switched transactions, such that a system controller coupled between the master device and the slave device, upon receipt of the request, immediately schedules the datapath between the master and slave devices and suspends other, competing transactions to execute the data transfer. The states of other transactions are stored, and are restored upon completion of the circuit-switched transaction.

Abstract: A distributed computer network comprising of unconfigured network home client computers, and at least one autoconfiguration server. The network may also include sales servers and local service provider servers. The home network client computer determines on power on time if it possesses the requisite configuration information. If the requisite configuration information is lacking, the home network client computer sends a configuration request along with client computer identifying information to the autoconfiguration server. On receiving the configuration request from a home network client computer, the autoconfiguration server uses the client identifying information to determine the local service provider information and client computer specific data. The autoconfiguration server determines the local service provider information by looking up a directory of local service providers, the directory being stored on the autoconfiguration server or on some local service provider server.