Abstract: The present invention teaches a variety of methods, data structures, and apparatus. In a first embodiment of the present invention, an instance of a data type has a data structure including a transient value data field for storing an internalized data format representation of a persistent data associated with the instance and a persistent value data field for storing an externalized data format representation of the persistent data associated with the instance. The data structure provides a capability of maintaining a persistent data associated with the instance within a database in which the data type of the instance is foreign. This includes embodiments in which the database is a relational database or an object oriented database. In some embodiments, the instance is included in a persistent programming language object.

Abstract: Protocol agents involved in the performance of global coherency activity detect errors with respect to the activity being performed. The errors are logged by a computer system such that diagnostic software may be executed to determine the error detected and to trace the error to the erring software or hardware. In particular, information regarding the first error to be detected is logged. Subsequent errors may receive more or less logging depending upon programmable configuration values. Additionally, those errors which receive full logging may be programmably selected via error masks. The protocol agents each comprise multiple independent state machines which independently process requests. If the request which a particular state machine is processing results in an error, the particular state machine may enter a freeze state. Information regarding the request which is collected by the state machine may thereby be saved for later access.

Abstract: A circuit for comparing a first digital word to a second digital word includes a precharge circuit to generate an initial match signal, an initial inverse match signal, and a virtual ground signal in response to an input clock signal and an inverse input clock signal. Each comparison circuit of a set of comparison circuits generates a computed match signal and a computed inverse match signal based upon a selected bit of the first digital word and a corresponding selected bit of the second digital word. A signal differential sensing circuit derives a match signal for the first digital word and the second digital word based upon the virtual ground signal, the input clock signal, the computed match signal, and the computed inverse match signal.

Abstract: A name service system in a computer network has a program on a master host which includes a name service map containing the names and corresponding network addresses of servers running in the network. The name service system also includes a proto-server residing on all hosts in which a server needing dynamic name service updates runs. The network address in the name service map corresponding to the server's name is the network address of a program called a "proto-server". The proto-server contains a name table having the name and the corresponding actual address of the server. The name table in the proto-server can be updated dynamically, and the proto-server enables multiple instances of similar servers to run on the same host. When a client requests the binding of a server from the name service, the client program determines whether the address returned from the name service map is the binding of the proto-server, and if so the binding in the proto-server's name table is fetched and returned to the client.

Abstract: In a system and method for managing repeated lock requests to synchronize an object with a particular thread, each lockable object has a lock datum and each thread can repeatedly request a lock for an object without knowing whether the thread is already synchronized with the object. Associated with each thread are a pair of locking registers and a pair of stack data structures. The registers reference the last object whose lock was acquired by the thread and contain a redundancy count indicating the number of consecutive lock requests for the object. The stack data structures contain references to other objects that are currently synchronized with the thread and an associated redundancy count for each such object. A locking procedure acquires the lock of an object only if a reference to the object is not contained in the registers or the stack data structures.

Abstract: A method and apparatus for performing signature analysis of video data being output by a RAMDAC so that starting and stopping the sampling of data is made precise so that the data sampled is a known set. The invention uses a timing generator and signature analysis hardware integrated with a RAMDAC to start and stop the sampling and signature calculation of video data on frame boundaries. A signature capture request bit is used to request that the next frame be sampled and a signature calculated. The hardware waits until the beginning of the next frame starts, and then samples data until the frame ends. The calculated signature is made available in a signature analysis result register for reading. The resulting signature is held in the signature analysis result register until cleared or another signature capture request is made.

Abstract: The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e.

Abstract: A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node. Because the memory space where the kernel resides is designated as local space, no other nodes can write to, or corrupt, the node's kernel.

Abstract: A four transistor XOR or XNOR gate includes an inverting stage and a non-inverting stage. The transistors in each stage are coupled so as to enable changing inputs and existing inputs to drive the output in the same direction. The XOR gate and XNOR gate take advantage of a known order or inputs to reduce the delay of the gate.

Abstract: Interconnection subsystems having diverse topologies are disclosed for interconnecting small numbers of nodes having a predetermined maximum degree in a multiprocessor computer system. The interconnection subsystems are generally classified into three diverse classes of topologies, including a "polygonal" class, a "ladder" class and a "tiled" class. In topologies of the polygonal class, a majority of the nodes in the multiprocessor computer system are connected in a ring and the remaining nodes are connected to the nodes in the ring, and in some cases also to each other. In topologies of the ladder class, the nodes are interconnected in a "ladder" topology comprising a series of nodes connected in a ring, the ring corresponding to one standard of a ladder topology folded on itself. Each node in the ring is connected to another node in a second series, effectively forming rungs of the ladder topology.

Abstract: A number of storage units and a number of state machines are provided to reorder interleaved ATM data cells for a number of channels incoming to a networked host computer. The storage units store the incoming ATM data cells, a number of data structures tracking the stored ATM data cells for the channels and the free resources, and an unload schedule queue. The state machines load and unload the incoming ATM data cells, and update the tracking data structures and schedule queue accordingly.

Abstract: A multiprocessing system having a plurality of processing nodes interconnected by an interconnect network. To optimize performance during spin-lock operations, a home agent prioritizes the servicing of read-to-own (RTO) transaction requests over the servicing of certain read-to-share (RTS) transaction requests, even if the RTO transaction requests are received by the processing node after receipt of the RTS transaction requests. In one implementation, this is accomplished by providing a first queue within the home agent for receiving RTO transaction requests conveyed via the interconnect network which is separate from a second queue for receiving RTS transaction requests. The queues may each be implemented with FIFO buffers.

Abstract: A computer system includes a data processor, a primary translation lookaside buffer for storing page table entries and translating virtual addresses into physical addresses, local memory coupled to the data processor for storing data and computer programs at specified physical addresses, and remotely located memory coupled to the data processor by a computer network for storing data at specified remote physical addresses. The computer system further includes a remote translation lookaside buffer (RTLB) that stores a plurality of remote page table entries. Each remote page table entry represents a mapping between a range of physical addresses and a corresponding range of remote physical addresses. The primary translation lookaside buffer translates a virtual address asserted by the data processor into a physical address.

Abstract: A keyboard contains an input device comprising a linear strip of sensitive material the approximate width of the human finger integrated into the left or right side of the keyboard. The strip is linearly sensitive in only one direction and not to any other direction, such as from left to right. A user operates the device by touching it with his or her finger and varies the input by changing the position along the strip and the pressure of his or her finger.

Abstract: A bit map is maintained by a provider object of a name server to keep track of names cached by a cache object of the client. The bit map is indexed by performing a hash of the name. When a name is looked up by the server on behalf of a client, the server hashes the name, and sets the bit in the bit map indexed by the result of the hash modulo the size of the bit map. The result of the hash is returned to the client and is stored with the entry in the cache. A bit "set" in the bit map indicates that the client caches at least one name that hashes into the bit. When the server invalidates a name, a hash of the name to be invalidated is used to find the corresponding bit in the bit mask. If the bit is set, the server sends an invalidation request to the client. The invalidation request includes the result of the hash, and the size of the provider's bit map. The client invalidates all entries that hash into the specified bit in the bitmap on the server.

Abstract: A method and apparatus for tracking pipeline resources of a processor involves fetching selected ones of the coded instructions and marking the fetched instructions with instruction metadata. The instruction metadata indicates a number of pipeline resources required by each instruction. The marked instructions are issued from the fetch unit and, using the instruction metadata, a count of a number of resources committed to issued instructions in the execution pipelines is maintained. When it is determined that the number of resources committed to issued instructions exceeds a preselected maximum and instructions are prevented from issuing from the fetch unit. As each instruction is retired, the instruction metadata is used to determine a number of resources released by retirement of the issued instruction.

Abstract: A technique for automating the assembly of networked, language independent objects into a network application for use in a distributed object computing system uses program templates and a symbol table. A schematic representation of the network application is formed within a visual application builder. The schematic representation defines connections among representations of previously defined distributed objects. These connections are formed among parts, plugs and sockets that are associated with representations of distributed objects termed components. The schematic representation of the network application is loaded into a symbol table and portions of the schematic representation are stored as a number of entries in the symbol table. These entries include identifier-value pairs; that is, identifiers are mapped to values. The program source files to be generated are determined and the program templates for use in generating the program source file are also determined.

Abstract: A central processing unit of a computer includes an external cache controller and a primary memory controller. The external cache controller generates a primary memory read request and a primary memory write request in response to an external cache miss. The primary memory controller includes an address queue, an eviction buffer, and an eviction buffer logic circuit. The eviction buffer logic circuit selectively stores the primary memory write request in the eviction buffer and stores the primary memory read request in the address queue. When subsequent primary memory read requests are received at the primary memory controller, the eviction buffer logic circuit routes them to the address queue. The primary memory write request in the eviction buffer is passed to the address queue when the eviction buffer logic circuit identifies an empty queue, meaning there are no pending primary memory write requests.

Abstract: An apparatus for facilitating the sharing of memory blocks, which has local physical addresses at a computer node, between the computer node and an external device. The apparatus includes snooping logic configured for coupling with a common bus of the computer node. The snooping logic is configured to monitor, when coupled to the common bus, memory access requests on the common bus. There is also included a snoop tag array coupled to the snooping logic. The snoop tag array includes tags for tracking all copies of a first plurality of memory blocks of the memory blocks cached by the external device. Further, there is included a protocol transformer logic coupled to the snooping logic for enabling the apparatus, when coupled to the external device, to communicate with the external device using a protocol suitable for communicating with the external device.

Abstract: A client computer system and associated method in a computer network over which are provided programs with methods. The client computer is capable of executing the programs with reduced run-time memory space requirements. Specifically, a network communications interface receives the methods of the programs and a network communications manager loads uncompressed in available space in the run-time memory the methods when they are received. An execution controller controls execution of the programs so that the methods are invoked and not invoked at various times during execution of the programs. A compressor compresses in the memory compressible ones of the uncompressed methods that are not invoked so that space is made available in the run-time memory. The compressor also decompresses in available space in the run-time memory decompressible ones of the methods so that they may be invoked.