Abstract: A transaction device driver that exports a transaction interface tailored to the requirements of conventional journaling file systems. The operating system file system informs the transaction device driver when a file system operation begins and ends and also informs the transaction driver about important data updates which have occurred since the beginning of the file system operation. The transaction device driver logs the updates as the data appears through the normal read/write/strategy entry points into the driver and, should the system fail while there are outstanding operations, ensures that either all of the changes for the operation will appear in the file system or that none of the changes will appear.

Abstract: A system and method provide transparent integration of a smart card private key operations with an existing set of encryption services and system applications. A key store manager manages user key data, and handles requests for key operations from the system applications. A user information file stores user data, including user private keys for users that do not have smart cards, and an indication of those users that have smart cards. A set of system applications interfaces with the key store manager through encryption protocol specific application programming interfaces. Users connect to the system through terminals or remote computers that may be equipped with smart card readers. For users having smart cards, the key store manager forwards to the smart cards requests for private key operations, such as encryption or decryption with the user's private key, from the system applications. In this manner the user's private key cannot be compromised by exposure to the computer system.

Abstract: A virtual file system accessing subsystem is disclosed for use in connection with a computer system connected in a computer network. The computer system runs a selected operating system, such as Microsoft's MS-DOS and Windows operating systems. The virtual file system accessing subsystem facilitates the accessing of a virtual logical storage device that is identified by a virtual logical storage device identifier and that has a virtual logical storage device file system that includes at least a portion of a remote file system maintained by another device connected in the computer network. The virtual file system accessing subsystem comprises an operating system request redirector for enabling the operating system to direct access requests from an application program which identify the virtual logical storage device to a remote access element for processing.

Abstract: The present invention provides a cache manager (CM) for use with an address translation table (ATT) which take advantage of way information, available when a cache line is first cached, for efficiently accessing a multi-way cache of a computer system having a main memory and one or more processors. The main memory and the ATT are page-oriented while the cache is organized using cache lines. The cache includes a plurality of cache lines divided into a number of segments corresponding to the number of "ways". Each cache line includes an address tag (AT) field and a data field. The way information is stored in the ATT for later cache access. In this implementation, "waylets" provide an efficiency mechanism for storing the way information whenever a cache line is cached. Accordingly, each table entry of the ATT includes a virtual address (VA) field, a physical address (PA) field, and a plurality of waylets associated with each pair of VA and PA fields.

Abstract: A method and apparatus for determining data dependencies and enabling bypass logic in parallel. In particular, a given stage in a given execution unit will (1) compare its destination register to the destination registers of the initial stage in each execution unit, and (2) combine the result of the comparison with the propagated results of preceding stages in the given execution unit. The other stages are not checked, as this is covered by similar checking logic in the earlier stages, with the results being passed on to the subsequent stages.

Abstract: An improved junction transistor requiring low power and having high performance is described. The transistor includes a substrate, a well region of a first conductivity type, and source and drain regions of a second conductivity type separated by a channel region. The transistor further includes a gate region positioned on the surface of the substrate over the channel region, and a buried region of the first conductivity type is positioned within the well region and below the surface of the substrate. The buried region has a dopant concentration of the first conductivity type sufficiently high to slow the growth of source-drain depletion regions and diminish the likelihood of punch through. The buried region may take the form of a buried electrode region or a retrograde well in alternate embodiments. The device is characterized by a gate threshold voltage of at most about 150 mV which can be electrically adjusted using back biasing or floating gate techniques.

Abstract: A method and apparatus processes a video image signal to generate one or more random number generator seeds. Preferably, the video image signal represents a scene that is both unpredictable and "live". As a result, potential interceptors of signals encrypted with a random number sequence derived from the seed will find it difficult, if not impossible, to determine the random number sequence. To further obscure the random number sequence from potential interceptors, a seed derived by processing a first video image signal is determined and is stored. Then, a second video image signal is received and a third video image signal is received. A difference is determined between the third video image signal and the second video image signal. If the difference exceeds a threshold (indicating that the scene represented by the video image signals is "live"), then the third video image signal is processed to generate a seed.

Abstract: A system and method provide transparent access from any system entry service to multiple account management services, and particularly to multiple authentication services on a computer system, supporting unified login and logout. Transparency between system entry services and account management services, including authentication, password, account, and session services, is provided by an application programming interface and a configuration file. The configuration file stores associations between system entry services, and selected account management services, and allows an individual system entry service to be associated with multiple different ones of a given type of account management service, such as authentication services.

Abstract: High speed scan testing is facilitated by pipelining or distributing a scan enable signal to scan circuits through a distribution network. The pipeline is formed from a plurality of scan enable distribution circuits residing on an integrated circuit to be scan tested. Preferably, before reaching the scan circuits, the scan enable signal passes through an equal number of the scan enable distribution circuits. The distribution network of the scan enable distribution circuits take a multitude of forms. The invention allows at-speed toggling of a scan enable signal as well as shifting of test data at functional system frequencies, while maintaining compatibility with test modes such as IEEE Standard 1149.1. The invention is also capable of supporting skewed-load and broad-side delay test modes.

Abstract: A method, apparatus, and computer-usable medium for compressing data in a file system utilizing the concept of "holes". A mapping table in a file system maps the logical blocks of a file to actual physical blocks on disk where the data is stored. Blocks may be arranged in units of a cluster, and the file may be compressed cluster-by-cluster. Holes are used within a cluster to indicate not only that a cluster has been compressed, but also the compression algorithm used. Different clusters within a file may be compressed with different compression algorithms. A unit of data is compressed, with the result that the file occupies fewer physical blocks than it has logical blocks. The mapping table is updated to indicate that for a given unit of data compressed, fewer physical blocks are needed. Certain logical blocks belonging to this unit of data are not mapped to physical blocks but are mapped to a hole.

Abstract: A position sensing apparatus has an insulating body with an interior surface defining a void within the insulating body. Electrodes extend through the body and terminate as electrical contacts on the interior surface. Two non-mixing fluids with distinct electrical properties are positioned in the void. This results in a first set of electrical signals on a first set of electrical contacts and a second set of electrical signals on a second set of electrical contacts. The first set of electrical signals and the second set of electrical signals specify a first angular inclination value (pitch) and a second angular inclination value (roll) characterizing the position of the sensing apparatus.

Abstract: A system and method are provided for controlling the generation of assembly language sequences. This is accomplished with a high level language which has as data types various elements of assembly language syntax. Included among the data types are "instructions" data types which specify variables having one or more assembly language instructions, e.g., floating point addition, integer load, conditional branch, etc. The grammar of the high level language permits variables of data type "instruction" to be output in standard assembly language syntax. By incorporating variables of assembly language data types, the language allows programmers employing functions, branch control, and other commonly employed programming techniques to write a programs which generate a large number of assembly language instructions in a controlled sequence.

Abstract: An apparatus and method for transferring data within a computer includes a first computer sub-system connected to a second computer sub-system. The first computer sub-system produces data that is passed to the second computer sub-system. The second computer sub-system includes error detection circuitry to identify an original error in the passed data. The original error is identified with a first error identification technique, such as an error correction code technique. The second computer sub-system also includes error perpetuation circuitry to perpetuate an error in the data as it is passed to another computer sub-system. The error perpetuation circuitry perpetuates the error according to a second error identification technique, such as a parity bit error technique. The original data error is thereby perpetuated by converting it to the error identification format used by the computer sub-system to which the data is transferred.

Abstract: Systems and methods for traffic control use scanning transmissometers to determine visibility along an extended stretch of roadway. When areas of decreased visibility are detected, such as dense localized pockets of fog, appropriate warning information is provided to drivers over warning devices positioned along the roadway. Information from the transmissometers is used to develop a speed profile, that is an indication of safe speed as a function of position along the roadway. Traffic sensors detect variations in behavior from that specified by the warning devices, such as a very slow vehicle, and modifies the warning information according. A computer readable medium contains a computer program for implementing the systems and methods.

Abstract: A backward compatible addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers. The computer system of the present invention has a processor capable of manipulating numbers having precision S, where S is a power of 2. The memory locations are specified in an instruction address field by an n-bit logical address ##EQU1## Each S-precision number is stored in a group of S memory locations accessed by an m-bit physical address ##EQU2## Each memory location is capable of storing a single precision number. Addressing logic for addressing the memory locations with the logical addresses includes alignment logic for setting:d.sub.i =0 for 0.ltoreq.i.ltoreq.(log.sub.2 S)-1,and settingd.sub.i =e.sub.i for log.sub.2 S.ltoreq.i.ltoreq.n-1;and extension logic for settingd.sub.i =e.sub.i-nfor n.ltoreq.i.ltoreq.m-1.

Abstract: In a computing system, debug flags for software development, testing, and debugging of a module of the operating system are retrieved and set. The module under development is provided with a debugging message handler and a lookup table of debugging flags. The table maps the debugging flags to memory locations containing the present state of the flags. A debugging message is generated at the application-level by a user desiring to monitor or alter the state of the debugging flags. The debugging message handler decodes the debugging message using the table, and the module reports or alters the debugging flag accordingly. In this manner, real-time program evaluation and control can be achieved without the conventional debugging software packages.

Abstract: A method and apparatus for fast and cost-effective digital video decompression is disclosed. The invention implements the inverse quantization, inverse discrete cosine transform and motion compensation functions for an MPEG decoder in a pipelined parallel processor. The IDCT and motion compensation functions are implemented to maximize parallelization by using partitioned arithmetic and logic operations in a superscalar microprocessor. This approach drastically reduces the total number of instruction cycles required to perform the IDCT and motion compensation functions.

Abstract: A remote power key function is implemented between a remote input device having a power key and a host computer system using a four lead USB interface. Normal functioning of the USB interface and of the input device are not affected. An input device includes a remote logic circuit comprising a transistor, a diode, and a low voltage battery. The remote logic circuit and MPU receive a first input from the power key and battery and receives a second input from the host-computer provided power supply that is "1" if the host computer is powered-up, and is "0" otherwise. Remote logic circuit output is coupled to the D+ USB interface line, and MPU output is coupled to the D+ and D- interface lines. Clamping latch logic within the host computer has a first input that is the D+ line, and a second input that is the power supply "1" or "0" signal. Latch logic output is input to the latch input port of the host computer power supply.