Abstract: A method and apparatus for checking for portions of record variables that are referenced before they are assigned a value. This checking occurs in the semantic checking portion of a compiler for a high level computer language. The present invention creates certain entries in a name list table (the symbol table) that point to two additional lists: the flist (fields list) and the clist (component list). The semantic analyzer refers to the name list table and to the clists and flists to determine whether a portion of a record variable has been assigned a value. If no value has been assigned to the portion of the record variable, the compiler prints an error message.

Abstract: A technique is disclosed for interlocking FIFO data paths. The data paths are interlocked using a series of control elements which receive input signals not only from the other control elements of their own path, but also from control elements of an adjacent data path. Queues may also be employed between the FIFO control chains to provide greater freedom in the interlocking mechanism.

Abstract: Unattended initialization of client disks according to foreign operating systems is supported. The data written on the client disk is provided from a server disk across a local area network (LAN), rather than from floppy disks. The client system is booked over the LAN with a first, network-oriented operating system, such as the UNIX-based Solaris.TM. operating system developed by Sun Microsystems, Inc. Solaris.TM. is then used to format the client disk. This formatting is done according to the file access table (FAT) file system. Then Solaris.TM. copies a disk image to the client disk from the server disk via the LAN. The disk image copied includes a second, client-oriented operating system, such as Windows.TM. that uses the FAT file system. Then the client system is rebooted with Windows.TM.. Network services, such as naming services or remote file access, can then be provided to Windows.TM. running on the client by Solaris.TM. running on the server.

Abstract: A technique for managing a network by sharing information between distributed network managers which manage a different portion of a large network is disclosed. By sharing such network information, the network management performed by the distributed network managers can inform site managers not only local network conditions but also about network conditions on other remote networks. A filtering operation is used to determine that portion of the network information deemed important to forward to another network manager. A database synchronization operation is also optionally provided so that databases of each network manager, which store topology information concerning the particular portion of the network, can be automatically synchronized.

Abstract: An interconnect controller for use in an arbitrary topology collection of nodes in a network suitable for use for both data sharing and distributed computing. The interconnect controller provides four (4) serial ports and two (2) parallel ports for communicating with adjacent nodes in a network. Linked ports between two nodes provide a continuous stream of information with idle packets filling non-data transfer cases. The logic of the interconnect controller provides for adaptive routing and to topology independence and allows for the sharing of a common clock for synchronizing the packet transmission.

Abstract: An apparatus for comparing and validating digital words uses a single dual-logic transistor arrangement to execute comparison and validation functions. A validation dual-logic circuit is achieved with a first configuration of input connections to the dual-logic transistor arrangement. The validation dual-logic circuit identifies a valid state between a valid bit of a first digital word and a valid bit of a second digital word. A comparison dual-logic circuit is achieved with a second configuration of input connections to the dual-logic transistor arrangement. The comparison dual-logic circuit identifies a match between a selected bit of the first digital word and a corresponding bit of the second digital word. The number of comparison dual-logic circuits used corresponds to the bit length of the digital words being compared. A single output node generates a match signal when the first and second digital words are identical and the validation function is satisfied.

Abstract: A significant reduction in the latency between the time the addressed components of memory are ready and the time addressed data is available to the address components of memory is achieved by processing the raw address information faster than the addition used in the prior art. XOR memory addressing replaces the addition of the base and offset address components with an XOR operation, eliminating carry propagation and reducing overall latency. In another embodiment, a sum-addressed memory (SAM) also eliminates the carry propagation and thus reduce the latency while providing the correct base+offset index to access the memory word line corresponding to the correct addition; thus a SAM causes no XOR duplicate problems.

Abstract: In the tagged, hashed file system, each finite portion of a file of the user's data is tagged with a pathname (filename and path) and a logical offset of the data within the file. A hint, as to where the portion is located in storage in the THFS, is computed by hashing the pathname and the logical offset. Once the hint is provided, then the THFS commences to search storage from the location suggested by the hint until it finds a match between the tag on the portion with the pathname and logical offset. When a portion is to be written, the intended location for placement of the portion must be read to ensure that it is available for writing, i.e. empty. If the location is not available, then a search must be made for the closest available (empty) location, and the user data is written there. If during a read operation a matched tag is not found until an empty area is read, the search will terminate, and the user application will be notified that no file was found.

Abstract: An architecture for an extended multiprocessor (XMP) computer system is provided. The XMP computer system includes multiple SMP nodes. Each SMP node includes an XMP interface and a repeater structure coupled to the XMP interface. The SMP nodes are connected to each other by unidirectional point-to-point links. The repeater structure in each SMP node includes an upper level bus, one or more transaction repeaters coupled to the upper level bus. Each transaction repeater broadcasts transactions to bus devices attached to a lower level bus, wherein each transaction repeater is coupled to a separate lower level bus. Transaction repeater includes a queue and a bypass path. Transaction originating in a particular SMP node are stored in the queue, whereas transactions originating in other SMP nodes bypass the incoming queue to the bus device. Multiple transactions may be simultaneously broadcast across the point-to-point link connections between the SMP nodes.

Abstract: A system and method for automating workflow by distributing the tasks required for the execution of said workflow over servers and clients connected on a network. The disclosed system and method allow the stages of the workflow to be performed asynchronously, meaning that, once a workflow initiated by a user has been initiated by a database server, the stages of the workflow can be executed on respective network clients without further interaction with the server (i.e., without requiring a stateful connection between the clients and servers). This is accomplished through the use of a workflow courier that embodies all programs (encompassing rules governing the execution of the workflow) and forms needed by clients to complete stages of the workflow. The workflow courier also stores workflow state information that indicates which stages of the workflow have been completed.

Abstract: A heatsink is pressure compliantly mounted against a substrate-mounted packaged electronic device such that the heatsink is not readily dislodged from the device package. A layer of pressure-compliant elastomeric foam material is sandwiched between the upper surface of the heatsink and an overlying shroud, which biases the heatsink downward toward the packaged device, which may be a BGA-packaged device. The lower heatsink surface is attached to the upper device package surface with double-sided thermal tape, and the shroud is attached to the substrate and compressively but compliantly urges each heatsink into more intimate thermal contact with an underlying device. The pressure-compliant material compensates for dimensional vertical tolerances associated with the substrate-mounted devices and heatsinks, while dampening vibrations and minimizing stress and torque that could otherwise damage the devices and/or the integrity of their electrical connections to the substrate.

Abstract: An apparatus and method for separating the design and implementation of a user interface ("the user interface logic") from the design and implementation of the functional portion of a software program (the "core logic"). The present invention uses an object-oriented programming model in which one or more look and feel agents act as servers for one or more logic objects. The look and feel agent controls the appearance and behavior of the user interface, while a logic objects perform the functions of the software program. A look and feel agent does not "know" what functions constitute the core logic and the logic objects do not "know" what the user interface looks like or how it behaves.

Abstract: An adjustable threshold voltage MOS device having an asymmetric pocket region is disclosed herein. The pocket region abuts one of a source or drain proximate the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. An MOS device having such pocket region may have its threshold voltage adjusted by applying a potential directly to its pocket region. This capability is realized by providing a contact or conductive tie electrically coupled to the pocket region. This "pocket tie" is also electrically coupled to a metallization line (external to the device) which can be held at a specified potential corresponding to a potential required to back-bias the device by a specified amount.

Abstract: An address translation control circuit which operates in connection with a processor and a translation look-aside buffer ("TLB") to perform virtual-to-physical address translations through shared entries of the TLB. The address translation control circuit comprises a primary context storage element, a group context storage element, a context matching circuit, a comparing unit and a logic unit. The context matching circuit is coupled to primary and group context storage elements to receive their context numbers and reads a context identification number and a context select bit value from a chosen translation entry of the TLB. Concurrently, the comparing unit compares the virtual address contained in that entry with the virtual address requested for translation by the processor. The logic unit receives the outputs from the context matching circuit and the comparing unit and signals operating system software whether an appropriate translation has been found in the TLB.

Abstract: The present invention signals the power on, mated, and activity status of storage units in a console rack-mounted memory system. The status is signalled using parallel-coupled LEDs activated by logically combined signals provided by a logic circuit using signals available from SCA connector pins that connect the storage units to the console rack. The SCA connector provides MATED1 (pin 44), MATED2 (pin 74), and LED ACTIVE (pin 77) signals that are logically ANDed by the logic circuits. A logic circuit lights an associated parallel-coupled LED pair for a storage unit when LIT=MATED.multidot.ACTIVE LED, where MATED=0 denotes grounded pins 74 and (optionally) 44, and ACTIVE LED=0 denotes grounded pin 77, and LIT=l denotes lit LEDs. A steadily lit LED pair denotes that a storage unit is mated into the console rack and is inactive. An intermittent LED pair denotes that the storage unit is mated into the console rack and is presently active (and thus should not be removed).

Abstract: A bracket for an electronic card that is inserted into a slot of a chassis. The chassis has a pair of opposing walls with guide channels that guide the card into a motherboard. The bracket includes a pair of low friction guide rails that slide along the guide channels. Attached to the guide rails are a pair of grommet dampers which are pressed between the edges of the card and the guide channels when the card is inserted into the chassis. The grommets dampen any shock or vibrational load that is transferred from the chassis to the card. The bracket also has a pair of spring clips that are attached to the card and pressed into the guide channels to provide an electrical path between the card and the chassis. The electrical path discharges electrostatic charges on the card and provides a ground path for any electromagnetic fields generated or received by the card. The bracket further includes a lever pivotally connected to one of the guide rails.

Abstract: A user-friendly editor for structurally represented computer programs is disclosed. The present editor combines advantages of text editors and structure editors by transforming, as the user types, the text stream entered by the user into a token stream, where the tokens of the token stream constitute the words of the program being entered. Each of the tokens is classified by the editor as one of group of extended lexemes defined by the language in which the program being edited is written. These extended lexemes are defined similarly to lexemes that might be used in a batch lexer, but are more numerous as the present editor must account for the incomplete and ill-formed lexemes that arise as the user types the program. Based on information in the token stream, the editor prettyprints the program as the user types.

Abstract: A hierarchial bus structure having at least three dimensions provides improved interconnect flexibility between nodes located on one or more levels of the structure. Nodes are defined on at least first and second "horizontal" (or "H") rings, the rings being coupled by at least one "vertical" (or "V") ring. Each node is identified in terms of its (H,V) coordinates in the hierarchial interconnect structure, and an M-dimensional structure will provide an M-way multiplex unit at each node. For an M=3, e.g., three-dimensional structure, each multiplex unit has three-inputs, a Localout, a Vin, and an Hin input, and couples one of these inputs to an output port in response to a Local select arbitration signal. The output signal is coupled to Hout and Vout, and to Localin. Nodes on the same horizontal level will drive their Hin signal to Vout and Hout, whereas all other nodes receive the Vin signal.

Abstract: An electrical assembly that allows a plurality of electronic assemblies to be cooled by a number of fans. The assembly includes a housing which has a plenum chamber that is located between a rack chamber and a fan chamber. The rack chamber is separated from the plenum chamber by a backbone wall. The fan chamber is separated from the plenum chamber by a fan wall that is perpendicular to the backbone wall. The rack chamber contains a plurality of electronic assemblies such as hard disk drives. The fan chamber contains a plurality of individual fans. The fans induce an air flow from the rack chamber to the fan chamber through the plenum chamber. The plenum chamber provides a uniform pressure that induces an equal flow rate across each disk drive in the rack chamber. The fans are controlled by a control circuit which can detect the failure of one fan and increase the speed of the remaining fans to maintain the plenum chamber pressure.

Abstract: A directory system directs cache line access requests from processors in a multi-processor system with a shared memory system through a cache line states directory. The cache line states directory stores a state value that identifies a cache line shared states word. The cache line shared states word identifies the processor that owns the cache line and the state of access of each processor that shares access to the cache line. A state value encoder encodes a cache line shared state word into a state value and loads the state value into the cache line states directory. A state value decoder decodes the state value into a cache line shared state word for use by the cache line directory system in retrieving the cache line. A plurality of cache line tables are used with each cache line assigned to one of the tables. The cache line table stores a state value for each cache line shared states word stored in the table.