Abstract: Methods and apparatus for using a store allocate policy to eliminate the stale data problem in a direct mapped, write-through virtual data cache. A hardware mechanism provided by the present invention, ensures that a single cache location associated with more than one virtual address does not become stale with respect to the main memory. By using a store allocate policy along with a write-through virtual cache, each time a store miss occurs, the data cache location for which the store miss occurred will be updated with new data brought back from the main memory along with a new cache tag. The store allocate policy for a write-through virtual data cache is implemented by a data cache controller. Thus, using this cache policy, the cache is updated along with the main memory even after a store miss.

Abstract: A flexible, low cost range locking mechanism allows a process requesting a lock to place a lock upon any requested range within a resource of a computer system. Various processes may hold locks upon different ranges of a resource simultaneously. A particular range may also be locked by different processes that are able to share the range. A sub-lock represents a unique range of the resource and has begin and end points that identify that portion of the requested range to which the sub-lock corresponds. A locked range may include numerous sub-locks. Each sub-lock has a mode indicating whether the sub-lock represents a shared lock, an exclusive lock or other. Sub-locks also have an incremental counter indicating the number of processes that hold a read lock upon a region, a flag to indicate whether a process is waiting to lock the region, a queue for listing waiting processes and other attributes.

Abstract: A processor is disclosed. The processor relates to a processor having a register file of registers and a dispatch unit capable of issuing up to (i) instructions of a program per cycle to an execution unit having (z) pipelines, wherein some of the instructions specify certain ones of the registers in the register file as source operands and designate certain ones of the registers in the register file as destination registers. The processor also includes a memory for storing the registers of the register file, the memory having (N) access ports configured to access up to (N) registers per cycle, where (N) is less than a maximum number of register values that may need to be accessed during a cycle.

Abstract: The present invention provides a system and process for making use of pre-existing data-structures which represent a computer program, in a way which has the advantages of shortening the time and cost required to create a new version of the computer program. The pre-existing data-structure is modified to produce a shadow data-structure which contains only shadows of those elements or nodes of the pre-existing data-structure required to perform the tasks of the new version of the computer program. The present invention includes processes to make the data-structure of the original program shadowable; processes to use data from the original program compilation process in compiling the new version of the program, including processes to create a shadow data-structure; and processes to use the new version of the computer program along with the shadow data-structure to create the desired execution.

Abstract: Various versions of a computer file are provided without requiring copying the file or logging changed data, so that the files have consistent user data. A program module responds to a system call argument and allocates another node in file system tables and copies metadata information from the old node into the new node, so that both nodes contain the same data block allocation information. Portions of the module set shadow pointers in the old node to point to the new node, and in the new node to point to the old node. Changes to data are made with respect to the new node and fresh physical data blocks are allocated for the changed blocks. A method includes the steps of allocating a new node for storing file allocation information for another version of an existing file; logically connecting the new node to the existing node for file name and other purposes; and replacing node identification information in the directory with the new mode identification.

Abstract: An interface for transferring data via a PCI bus between a initiator device and a host target having a local cache buffer. The PCI interface to the local cache buffer includes an interface controller, an address resolution unit, data and address logic, byte enable logic and command processing logic. The command and data logics resolve address hits and misses and determine when a write operation will occur to the local cache buffer. The interface controller performs hand shaking operations between the PCI interface and an initiator device connected via the PCI bus. The interface controller also regulates the transfer of data between the device initiator and the local cache buffer, providing status and control signals to the cache controller during a given transfer cycle. The data logic receives the data from the PCI bus and verifies parity providing data and parity information to the cache buffer and cache parity error buffer.

Abstract: An automatic method and system for retrieving information based on a user-defined profile (e.g. a personalized newspaper). A user-controlled client establishes communication with a stateless server, the server presenting a list of options to the client between the server and the client. The client provides an identification of the user-defined profile. The server engages a first application program, the first application program retrieving the user-defined profile wherein the user-defined profile identifies information which is of interest to the user. The first application program examines a database of information and automatically retrieves a subset of the information from the database based upon which information is of interest to the user as identified in the user-defined profile. The server presents the subset of the information from the database as generated by the first application program to the client.

Abstract: A system and method for establishing a peer-to-peer communication connection between computer programs from the same security domain, but executing in first and second computers, is disclosed. A first computer program, while executing in the first computer, sends a communication a message to the second computer, requesting a peer-to-peer communication connection. Upon receiving the message at said second computer, the second computer determines whether a second computer program meeting predefined criteria for establishing a peer-to-peer communication connection is executing in the second computer. If so, the second computer sends to the first computer a reply message accepting the request. After receipt of the reply message by the first computer, the requested peer-to-peer communication connection between the first and second computer programs is established.

Abstract: A leaf type spring is used to hold a heat sink in contact with a chip or other heat-emitting component. Such a component may be mounted on a PCB or other element. A bolster plate is positioned below the PCB and two pins extend up from the bolster plate, through the PCB and through the base of a heat sink. A preferred heat sink has plural fins extending up from the base. In one form of the invention the pins extend above the level of the outer ends of the pins. A spring extends diagonally across the ends of the fins. Slots in the ends of the spring engage necks formed near the ends of the pins. In another form of the invention the fins are milled or otherwise formed with a groove extending diagonally across the heat sink and the spring fits into the slot. The pins extend only a short distance above the base of the heat sink and are necked to receive the slotted ends of the spring. In both forms of the invention intimate contact of the base with the heat emitting component improves heat transfer.

Abstract: A multiprocessor system has a plurality of processing cells, each including a processor and memory, interconnected via a network. The memories respond to requests by the processors for accessing data and, absent fault, transmitting it in response packets to at least to the requesting processors. A fault containment element responds to at least certain faults during access or transmission of a datum for including within the respective response packet a fault signal that prevents the requestor from accessing the datum. If a fault is detected in a datum not previously detected as faulty, a marking element can include a "marked fault" signal in the response packet. Whereas, it can include an "unmarked fault" signal when it detects a fault associated with a requested datum, but not specifically isolated to that datum. When a request is made for a datum which had previously been detected as faulty, the marking element can include in the response packet a "descriptor fault" signal.

Abstract: In summary, the present invention is a multithreaded computer system having a memory that stores a plurality of objects and a plurality of procedures. Each object has a lock status of locked or unlocked, and includes a data pointer to a data structure. The system uses a global object locking procedure to service lock requests on objects that have never been locked as well as objects that have not recently been locked, and uses a local object-specific locking procedure to service lock requests on locked objects and objects that have been recently locked. The global object locking procedure has instructions for changing a specified unlocked object's lock status to locked, and for creating for each specified object a local object locking procedure. The local object locking procedure includes a lock data subarray for storing the object's lock data and instructions for updating a specified object's stored lock data.

Abstract: A central processing unit with an external cache controller and a primary memory controller is used to speculatively initiate primary memory access in order to improve average primary memory access times. The external cache controller processes an address request during an external cache latency period and selectively generates an external cache miss signal or an external cache hit signal. If no other primary memory access demands exist at the beginning of the external cache latency period, the primary memory controller is used to speculatively initiate a primary memory access corresponding to the address request. The speculative primary memory access is completed in response to an external cache miss signal. The speculative primary memory access is aborted if an external cache hit signal is generated or a non-speculative primary memory access demand is generated during the external cache latency period.

Abstract: A method and apparatus for improving the performance of pipelined computer processors having fast clock speeds and processing cycles for performing signed and unsigned load operations to memory. A load instruction includes signed and unsigned variants. Signed load operations include accessing signed load data from memory, aligning and sign extending the value of the accessed data. The present invention provides two different schemes for scheduling the processor's pipelines to handle accessing signed and unsigned data from memory. The two schemes include a data dependent scheme that accesses data from memory where the sign of a load data is not known until the data has been accessed from memory, and an opcode dependent scheme when the sign value of data being accessed is known prior to accessing memory. In the data dependent scheme, the processor is scheduled to process a signed LOAD in two cycles if the load data is negative, and one cycle if the data is positive.

Abstract: A computer system which includes a processor having an instruction set capable of "delaying" block-store instructions related to any outstanding block-load instruction(s). Accordingly, a method for interleaving block data transfers and processing steps which exploits the characteristics of the instruction set and architecture of the processor in order to increase efficiency and throughput of the computer system is provided. Hence by interleaving the block-store instruction of the previous data block with the block-load instruction of the next data block, the entire block transfer process can streamlined.

Abstract: A client/server computer apparatus includes a large number of client computers connected to a transmission channel. The client computers generate method calls that are applied to the transmission channel. Each method call may be encoded with a different communication protocol. A server computer processes each method call from the transmission channel by initially locating within each method call a method descriptor specified in a protocol-dependent format. The method descriptor is then compared to a list of protocol-dependent values stored in the memory of the server computer. An index value is assigned upon matching the method descriptor to a selected protocol-dependent value in the list of protocol-dependent values. The index value is passed to a protocol-independent portion of the server computer. The protocol-independent portion of the server computer executes the method corresponding to the index value to generate a reply.

Abstract: A computer system has a program module verifier and at least first and second program modules. Each program module includes a digital signature and an executable procedure The first program module furthermore includes a procedure call to the second procedure module, a procedure call to the program module verifier that is logically positioned in the first program module so as to be executed prior to execution of the procedure call to the second program module, and instructions preventing execution of the procedure call to the second program module when the procedure call to the program module verifier results in a verification denial being returned by the program module verifier.

Abstract: A network interface circuit (NIC) is provided with logic for maintaining various control pointers and at least one control counter for controlling burst transferring of buffered ATM cells to its host computer system in a non-cellboundary-aligned block manner, distinguishing the ATM packet header from the ATM data most of the time, except for a number of predetermined exceptions. More specifically, ATM packet headers and ATM data are to be burst transferred to separate header and data buffers on the host computer system, except for short and atypical packets, in fixed size blocks, where the block size is complementary to the interface bus, but not necessarily aligned with the ATM cell boundaries. For the short and atypical packets, both the header and data are to be burst transferred into the header buffer instead.

Abstract: A component card interconnect apparatus for coupling a component card to a computer system. A component card includes a first group of in-line pins with first power pins for conveying a first voltage and a second group of in-line pins with second power pins for conveying a second voltage. The second voltage is lower than the first voltage. Either the first or the second voltage is conveyed at one time.