Abstract: Utilizing a register file only addressable as double precision registers for part of the register file for storing single precision register results. In particular, groups of data in addressable single precision registers are written as pairs using the double precision register address in the double precision register file. Subsequently, the same data can be written back to where they can be accessed as single precision data.

Abstract: An electronic device and method for utilizing two extra microcode instructions to generate a set of test patterns which provide complete bitwise self-testing of the on-chip memory of a microcode sequencer. The self-testing sequence can be triggered by a single external interface event.

Abstract: A multi-channel recursive interface having independent channels that can be used in, for example, multi-level memory systems is disclosed. Separate read and write command channels and read and write completion channels permit concurrent read and write operations. A memory system according to the present invention uses a write buffer to resolve read data ambiguity when concurrently reading and writing into the same memory location. With independent and asynchronous read and write channels, the interface of the present invention retains its properties even if separated from the system it interfaces by communication channels exhibiting any latency such as first in first out (FIFO) registers of arbitrary lengths. Such FIFOs can improve the throughput of the communication channels between the interface and the system it interfaces with. The recursive interface can flexibly serve many levels of memory.

Abstract: A client/server computer apparatus includes an aggregation of server computers connected to a transmission channel. The aggregation of server computers includes a dual-role proxy server computer, and a set of non-proxy server computers. A set of client computers is also connected to the transmission channel. The set of client computers generates remote procedure calls to objects that are stored on the aggregation of server computers. The remote procedure calls include non-client remote procedure calls to the dual-role proxy server computer and client remote procedure calls to the non-proxy server computers. The dual-role proxy server computer processes the client remote procedure calls only when the set of non-proxy server computers cannot process the client remote procedure calls. The processing of client remote procedure calls by the dual-role proxy server computer results in the passing of information so that the client remote procedure calls can obtain servicing from the non-proxy server computers.

Abstract: A method and apparatus for representing and storing the schedules of recurring events is provided. The schedules are represented by recurrence rules generated according to a specific grammar. According to the grammar, each recurrence rule is composed of one or more recurrence commands. Each recurrence command corresponds to a cycle and includes a time interval indicator that specifies the duration of the cycle and a repeat quantity that determines the number of times the cycle is repeated in the schedule. Each recurrence command may also include an occurrence list that specifies at what times during a particular cycle the event occurs. The occurrence list may specify times in absolute or relative terms. Thus, the grammar supports recurrence rules for representing the schedule "first and tenth of every month" as well as the schedule "second Thursday and last Friday of every month".

Abstract: A method and apparatus are disclosed which provide solutions to the problems which are encountered in an object oriented, distributed computer system in which attempts are made to monitor and display performance characteristics of objects in the system, where no prior knowledge of the objects exists. The invention disclosed herein is a generic monitoring and display system which can obtain performance data from and about objects and display the data in an appropriate manner without having to create special one time data acquisition and display programs, and which can select an appropriate display type based upon a display indicator contained in the captured data. Additionally, a tabular object is disclosed which can be used by operating objects to facilitate operating data collection and reporting.

Abstract: Computers are manufactured with connectors in which are inserted at least one PCI expansion card to increase the capacity of the computer. A computer enclosure panel is formed with an opening for insertion and withdrawal of the card. The card has a cover which blocks the opening after the card has been plugged in. The invention provides a retainer mounted on the rear panel which, when projected, engages the cover to assist in holding the card in place. The slide has a detent which is manually disengaged in order to slide the cover to retracted position. It further provides room for the tab conventionally extending outward of the card so that the card may be located closer to the side panel, thereby conserving space within the enclosure. Computers as shipped from the factory many times are not provided with PCI cards and the opening is blocked by a removable blanking cover. The slide also holds the blanking cover in position.

Abstract: In a pipelined processor, a method and apparatus for performing restoration of the previous values of young bits in the annex after a mispredicted branch has been detected. In a first embodiment, beginning with the oldest annex entry, the destination register address of that entry is broadcast to all other entries. All annex entries with matching addresses have their young bits reset, while the young bits of the broadcast entry is set. The above broadcast, compare, reset, and set operations are performed on all the remaining valid entries sequentially and in order of decreasing age. When all valid entries have been broadcast, the young bit states are correctly reconstructed. In a second embodiment, each annex entry has a current young bit Y0 and one or more past young bits (Y1 through YN). For branch condition resolutions which take up to N clock cycles, N past young bits are maintained in each annex entry.

Abstract: An improved single ended dynamic sense amplifier circuit for sensing the state of a bitline in a read only memory is disclosed which includes a threshold control circuit coupled to a noise margin circuit and a discharge circuit. A sense node couples the discharge circuit to a precharge circuit and an output circuit. The threshold control circuit maintains a bias on the discharge circuit such that during the precharge phase of operation, the discharge circuit is shut off and then conditionally turned off and on. The inclusion of the threshold control circuit in the disclosed single ended dynamic sense amplifier circuit provides for fully functional operation at supply voltages of close to 1.0 volt.

Abstract: A program interpreter for computer programs written in a bytecode language, which uses a restricted set of data type specific bytecodes. The interpreter, prior to executing any bytecode program, executes a bytecode program verifier procedure that verifies the integrity of a specified program by identifying any bytecode instruction that would process data of the wrong type for such a bytecode and any bytecode instruction sequences in the specified program that would cause underflow or overflow of the operand stack. If the program verifier finds any instructions that violate predefined stack usage and data type usage restrictions, execution of the program by the interpreter is prevented. After pre-processing of the program by the verifier, if no program faults were found, the interpreter executes the program without performing operand stack overflow and underflow checks and without performing data type checks on operands stored in operand stack. As a result, program execution speed is greatly improved.

Abstract: A user-friendly editor for structurally represented computer programs is disclosed. The present editor combines advantages of text editors and structure editors by transforming, as the user types, the event stream entered by the user into a token stream, where the tokens of the token stream constitute the words of the program being entered. Each of the tokens is classified by the editor as one of group of extended lexemes defined by the language in which the program being edited is written. These extended lexemes are defined similar to lexemes that might be used in a batch lexer, but are more numerous as the present editor must account for the incomplete and ill-formed lexemes that arise as the user types the program. Based on information in the token stream, the editor prettyprints the program as the user types. The editor also allows the user to edit the program from the prettyprinted display as if the program were internally represented as text.

Abstract: A method and apparatus of reporting the status of data transfer between software and hardware in a computer system is disclosed. Software provides empty descriptors to the hardware for posting completion updates of transfers. More particularly, the software provides the number of the last available descriptor to a first storage field in a storage location which is accessible to the hardware. The hardware accounts for the number of the descriptors it has used for reporting completion updates by posting the number of used descriptors to a second storage field in the storage location. To determine if more descriptors are available, the hardware compares the contents of the first storage field to that of the second storage field. If the contents of the first and second storage fields are equal, the hardware has reached the last descriptor in the completion ring. If the fields are not equal, one or more descriptors are available for the hardware to use.

Abstract: A shopping cart metaphor is emulated on a network of server and client computing systems. A browser at the client station has a request module to send a shopping page request to the server. A shopping page module in the server sends a shopping page file to the browser in response to the shopping page request. The shopping page file contains items selectable by a user using the browser. A shopping module at the browser generates an add request and sends the add request to the server. This add request contains selected items from the items that were selectable in the shopping page file. A receiver at the server receives the add request from the browser, and a cart list module at the server initializes a shopping cart list. An add module at the server adds the selected items to the shopping cart list.

Abstract: A system, method and computer program product of especial utility in providing a visual indication to a computer system user of the familiar "blinking", of pulsing, data access lights of conventional hardware data sources such as disk drives, CDROM drives and network connections in order to illustrate data cache "hits" and "misses" of an inherently computer program based caching function by incorporating simulated access lights as part of a graphical user interface ("GUI") for a data caching computer program. The GUI then allows a system user to intuitively visualize how effectively the data cache is functioning with respect to data which is accessed from the cache and data which must be accessed from another relatively more slow access time data source.

Abstract: A method for scaling images by a factor of two. Two variables are extracted from an unaligned input stream. The variables are selectively interleaved. The high and low order bytes of the results of the interleaving are multiplied to convert to a 16-bit representation. Horizontally interpolated data is generated by adding pairs of this conversion. The previous iterations of horizontally interpolated data is retained in buffers. Vertically interpolated data is formed by adding current and previous horizontally interpolated data together. The horizontally interpolated data is then doubled to maintain equal precision between the vertically and horizontally interpolated data. A packing function is employed to convert the data back to an eight-bit representation for output to the destination. Because the precision is the same, a single implicit divisor in the packing instruction handles both horizontally and vertically interpolated data.

Abstract: A dual-ported tag array of a cache allows simultaneous access of the tag array by miss data of older LOAD instructions being returned during the same cycle that a new LOAD instruction is accessing the tag array to check for a cache hit. Because a load buffer queues LOAD instructions, the cache tags for older LOAD instructions which missed the cache return later when new LOAD instructions are accessing a tag array to check for cache hits. A method and apparatus for calculating and maintaining a hit bit in a load buffer perform the determination of whether or not a newly dispatched LOAD will hit the cache after it has been queued into the load buffer and waited for all older LOADs to be processed. A load buffer data entry includes the hit bit and all information necessary to process the LOAD instruction and calculate the hit bits for future LOAD instructions which must be buffered.

Abstract: An improved graphical user interface for displaying and selecting video programs, such as video on demand, includes a video on demand server coupled to a communication medium. A plurality of settop box receivers are coupled to the communication medium for receiving digitized programming in the form of movies and the like from the video on demand server. The settop box includes a central processing unit (CPU) coupled to a memory and other electronic modules. The CPU generates and displays the present invention's graphical user interface on the subscriber's television. The graphical user interface is based upon a metaphor in which a world of spaces are organized as part of a studio back lot through which a user may navigate. The back lot includes a Poster wall which presents to the user a series of movie posters representing available selections.

Abstract: A generic Input/Output interface between an IO block and a System and ATM Layer Core on a network interface circuit is provided. The GIO interface includes parallel DMA read and write control handshake signal lines; parallel DMA read and write data handshake signal lines which operate independently from the read and write control handshake signal lines; parallel DMA read and write data signal lines; and a single clock signal line. GIO interface facilitates maximum utilization of the IO bandwidth, and allows several requests to be queued across the GIO interface at the same time, in each read and write direction. In addition, the GIO interface utilizes a fixed clock for driving the transmit and receive data path. By thus referencing all transactions to a clock driving the Core, the Core remains unchanged for different embodiments of the network interface circuit which interface to different host computer systems and busses.

Abstract: The present invention provides an improved Federated Naming Framework System which includes a Federated Naming Service Provider Interface ("FN SPI") for four (4) kinds of Name Services (Atomic Name, Compound Name, Partial Composite Name and Composite Name) along with a mechanism, designated the "FN Framework", which sits between the Client application and these Name Services and supports the translation and administration of calls for resolution of composite names to allow Client applications to make appropriate use of the available FN SPIs (there may be more than one FN SPI in any given system). The improved Federated Naming Framework System provides mechanisms to define and process strong and weak separation in the determination of naming system boundaries. Moreover, the present invention allows system implementors to install new naming services either statically or dynamically without disruption of the Client applications.

Abstract: A floating point processor for a 3-D graphics accelerator which includes improved performance over prior art designs. The floating point processor includes three specialized engines or function units which streamline floating point operations and which provide improved performance over prior systems. In the preferred embodiment, the floating point processor comprises a floating point core (F-core), a lighting core (L-Core), and a set-up core (S-core). Computations for triangles and vectors are split over the three function units for improved efficiency. The F-core processor receives geometry primitive data and performs floating point operations on the received geometry data. The L-Core processor comprises a fixed point computational unit for performing lighting computations. The set-up core comprises a fixed point computational unit for performing set-up calculations for geometric primitives.