Abstract: A software-based encoder is provided for an end-to-end scalable video delivery system that operates over heterogeneous networks. The encoder utilizes a scalable video compression algorithm based on a Laplacian pyramid decomposition to generate an embedded information stream. The decoder decimates a highest resolution original image, e.g., 640.times.480 pixels, to produce an intermediate 320.times.240 pixel image that is decimated to produce an intermediate 160.times.120 pixel image that is compressed to form an encodable base layer 160.times.120 pixel image. This base layer image is decompressed to form an image that is up-sampled by interpolation to produce an up-sampled 320.times.240 pixel image. This up-sampled image is subtracted from the intermediate 320.times.240 pixel image to form an error image that is compressed and encoded as a first enhancement 640.times.480 pixel layer. The decompressed base layer image is also up-sampled at step to produce an up-sampled 640.times.

Abstract: A terminating element is connected between the terminating ends of a transmission line pair. A switching mechanism coupled to the originating ends of the transmission line pair steers a constant current through the transmission line pair. In response to input control signals, the switching mechanism steers the constant current in a complementary fashion into one of the lines of the transmission lines pair to creates a differential output voltage across the terminating element. Controlling the differential voltage by manipulating current flow allows for acurate control over V.sub.OH and V.sub.OL levels. Since the terminating element is connected between terminating ends of the transmission line pair, nearly all of the constant current flowing the driver contributes to the differential output voltage, thereby reducing power undesirable power dissipation.

Abstract: An image alpha blending method utilizing a parallel processor is provided. The computer-implemented method includes the steps of loading unaligned multiple word components into a processor in one machine instruction, each word component associated with a pixel of an image; alpha blending the multiple word components of different source images and a control image in parallel; and storing the alpha blended multiple word components of a destination image into memory in parallel.

Abstract: The present invention supports allows an emulated environment to interface with a host environment, thereby enabling drag and drop functionality of the emulated environment to function in the host environment. The look and feel of an environment's drag and drop functionality is emulated in a host environment. A drag window is created from the emulated environment's drag image. Modifier keys of the host environment are mapped to those used in the emulated environment. Windows are registered for drag and drop in the emulated environment's registered windows database. The host environment's drag and drop database is updated to identify the registered windows of the emulated environment.

Abstract: An interprise computing manager in which an application is composed of a client (front end) program which communicates utilizing a network with a server (back end) program. The client and server programs are loosely coupled and exchange information using the network. The client program is composed of a User Interface (UI) and an object-oriented framework (Presentation Engine (PE) framework). The UI exchanges data messages with the framework. The framework is designed to handle two types of messages: (1) from the UI, and (2) from the server (back end) program via the network. The framework includes a component, the mediator which manages messages coming into and going out of the framework.

Abstract: A system and method for file system fix-on-panic for a computer operating system which comprises an enhancement to the UNIX.RTM. File System ("UFS") that increases total system availability by detecting file system errors and determining whether on-line repair is possible and then locking, repairing and unlocking the failed file system. Availability of the entire computer system is increased since the mean time to failure for independent threads is increased by the amount of time up to the next failure and the mean time to repair for dependent threads is reduced to only the amount of time necessary for the repair. The system and method disclosed allows for repairs to be made during use, may be called from the user level and allows for blocking of only particular threads.

Abstract: A processor processes a segmented to linear virtual address conversion instruction to convert segmented virtual addresses in a segmented virtual address space to a linear virtual address in a linear virtual address space. The segmented virtual address space comprises a plurality of segments each identified by a segment identifier, each segment comprising at least one page identified by a page identifier. The linear virtual address space includes a plurality of pages each identified by a page identifier. In processing the segmented to linear virtual address conversion instruction, the processor uses a plurality of segmented to linear virtual address conversion descriptors, each associated with a page in the segmented virtual address space, each segmented to linear virtual address conversion descriptor identifying the page identifier of one of the pages in the linear virtual address space.

Abstract: Methods and computer program products are disclosed for improving the performance of hardware and software in which checking for duplicates on a linked list is required. In one form, a linked list is checked in its entirety for the presence of duplicates. In another, an element to be added to the linked list is checked to determine whether a duplicate of that element exists on the linked list.

Abstract: A method for passing mastership of a bus is described. According to the method, it is determined whether to use the bus. If the bus is to be used, it is determined whether the bus is available. If the bus is available, the bus is accessed and a signal is generated to indicate that the bus is being accessed. A timer is also started and access to the bus is yielded when the timer expires. A processor that passes mastership to a shared resource is also described. The processor comprises a resource accessing unit. The resource accessing unit allows the processor to access a resource upon receiving a first signal from a component coupled to the resource. The resource accessing unit yields access of the resource to the component upon receiving a second signal from the component.

Abstract: A computer system and associated method for executing a plurality of threads of execution with reduced memory space requirements. The computer system comprises a memory, an execution controller, and a data compressor. The execution controller controls execution of the threads such that the threads are executable and unexecutable at different times. The execution controller also stores uncompressed into available space in the run-time memory execution data of the threads when the execution data is generated. The data compressor compresses the uncompressed execution data of compressible ones of the threads that are unexecutable. As a result, space is made available in the run-time memory. The data compressor also decompresses in available space in the run-time memory the compressed execution data of decompressible ones of the threads so that the decompressible ones of the threads may be executed after becoming executable.

Abstract: In a multiprocessor system having a shared memory, each central processor services copyback requests from other central processors. Each central processor has a writeback buffer along with a plurality of tag buffers and an associated snoop architecture for processing writeback and copyback commands. Each central processor includes a cache subsystem having a system interface, a main cache and an associated tag array. The system interface has an address controller and data controller, each having separate input and output queues for interfacing between the central processor and system control and data buses. The address controller includes a set of duplicate tags that mirror the tags associated with the main cache, and an auxiliary tag input buffer and auxiliary tag output buffer. The address controller has for each line in the output queue an associated pointer that indicates the location in the data controller where data is stored that is associated with output queued commands.

Abstract: A distributed object oriented computer system that has two classes of object references: strong references and weak references. Weak references (or pointers) allow users to refer to an object, but does not prevent the object manager from deleting the object. A weak object reference can be converted into a strong object reference by execution of a "MakeStrong" operation, which generates a strong reference, and then deleting the weak reference. A strong object reference can be converted into a weak object reference by execution of a "MakeWeak" operation, which returns a weak reference to the object referred to in the operation's argument, and then deleting the strong reference. When an object no longer has any outstanding strong object references, deletion of the object is enabled. In another aspect of the invention, a portion of the computer's memory is set aside for a primary linker cache and a secondary linker image cache.

Abstract: A high speed bus structure which makes the bus effective and practical to use for both single processor and multiple processor environments. This is achieved by providing an active bus wherein a number of logic functions which control the operation of the bus are removed from the modules and are centralized and incorporated into the bus. The amount of bus functionality provided by the modules is minimized therefore decreasing the complexity and computational overhead of the modules and traffic on the bus that are attributable to supporting the functionality to operate the bus. The number of bussed signal lines is minimized by eliminating the bussed lines relevant to the centralized bus functions. In place of the bussed signal lines, dedicated signal lines connect the modules inserted into the bus and the bus components providing the centralized logic functions.

Abstract: A method is disclosed for reusing directory search handles in a manner that minimizes the possibility that a handle allocated for a directory search request that is not yet complete will be reused. This method is implemented by assigning a block of system memory at the time of system initialization for the creation of a set of directory search and information retrieval handle structures. Handle structures within the set are allocated as they are needed. When all have been allocated, they are reused, one at a time in a least-recently-used fashion which gives preference to handle structures which have the lowest probability of being associated with an incomplete search request.

Abstract: This disclosure describes a solution to this basic problem of transaction management for systems which use the object metaphor to define the interfaces between different components of a system. An elegant solution is described which defines a transaction manager protocol and process, which is independent of the operating system micro-kernel's interprocess communication activities. The object-oriented transaction manager ("TM") creates transactions, keeps track of all object managers (servers) that are a part of a transaction, and coordinates transaction termination among all objects that are involved in the transaction. In addition, operations by naive applications can be made to execute under transaction control without modifying the applications.

Abstract: An arithmetic logic unit (ALU) with improved critical path performance includes two sets of adder circuits, a logic circuit, a set of multiplexors and a decoder. The adder circuits perform redundant add operations, one with a unit carry input and one without a carry input, upon multiple respective portions of the two sets of input signal bits. The logic circuit performs Boolean logic operations upon the two sets of input signal bits. In accordance with a set of selection control signals, the multiplexors select among the multiple results of such redundant add operations and Boolean logical operations for outputting as the final output bits. Such selection control signals are generated by the decoder based upon the contents of the two sets of input signal bits.

Abstract: An apparatus for generating a cell layout representative of a CMOS logic cell. The apparatus includes a pMOS transistor layout generator for generating a first set of layout data representative of a plurality of substantially similar pMOS relatively low strength transistor groups that are oriented along a first direction. The apparatus further includes an nMOS transistor layout generator for generating a second set of layout data representative of a plurality of substantially similar nMOS relatively low strength transistor groups that are also oriented along the first direction.

Abstract: Apparatus, methods, systems and computer program products are disclosed to provide a hypertext user with a history facility for displaying accessed hypernodes. The invention displays the history list to the user based on when the hypernode was accessed and based on the placement of the hypernode in the hyperlink hierarchy.

Abstract: A compiler requires normal exceptions that are throwable by a method to be either explicitly declared or else "caught" by appropriate exception handlers in the method to be compiled. This ensures that all normal exceptions thrown will be handled by a programmer specified exception handler. The compiler inspects all instructions in a specified method that throw exceptions and all instructions that invoke other methods, and determines whether each type of exception throwable by those instructions and invocable methods is (A) a serious exception (i.e., not a normal exception), (B) is caught by an enclosing exception handler, or (C) is explicitly declared in the method header of the specified method. If any throwable exception cannot be so categorized, that means the throwable exception is a normal exception that is not caught by an enclosing exception and is not explicitly declared in the method header, which means that the method to be compiled is not well formed.

Abstract: A novel video server is taught which allows for additional output bandwidth from the server by using multiple physical network interfaces over a single IP subnetwork. This approach is particularly well suited for use with video servers that store and deliver multimedia bit streams by allowing all clients to share the same subnetwork with the server. In this manner, the bandwidth from each of the physical network interface can be combined as needed and assigned as needed in service to any plurality of destinations in the network, allowing all bandwidth to be available for use with one or more clients.