Abstract: An improved technique for monitoring computer processes and their attributes using a three-dimensional graphical image. The three dimensional graphical image is formed by displaying the graphical objects associated with the computer processes and their attributes. The physical relationship between the various graphical objects within the graphical image preferably model the actual relationships between the processes and their attributes. The computers which run or activate the processes may also be represented by a graphical object within the graphical image. As the attributes of the computer processes change, the characteristics of the graphical objects are quickly adjusted and the three-dimensional graphical image is updated to reflect the changes to the attributes of the computer processes being monitored.

Abstract: Low threshold voltage MOS devices having buried electrodes are disclosed herein. Such devices have source and drain regions which include tip regions and plug regions. The buried electrodes have bottom boundaries located above the bottoms of the plug regions. The buried electrode has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. The exact dopant concentrations and locations of the buried electrodes should be provided such that punch through is avoided in MOS devices.

Abstract: A mechanism for implementing a store instruction so that a single cache access stage is required. Since a load instruction requires a single cache access stage, in which a cache read occur, both the store and load instructions of the present invention utilize a uniform number of cache access stages. The store instruction is implemented in a pipeline microprocessor such that during the pipeline stages of a given store instruction, the cache memory is read and there is an immediate determination if there is a tag hit for the store. Assuming there is cache hit, the cache write associated with the given store instruction is implemented during the same pipeline stage as the cache access stage of a subsequent instruction that does not write to the cache or if there is no instruction. For example, a cache data write occurs for the given store simultaneously with the cache tag read of a subsequent store instruction. This allows for a more uniform and efficient pipeline format for each instruction.

Abstract: A method and apparatus for handling multiplexer contention during scan. During a test scan of a multiplexer circuit, it is possible for multiple inputs of a multiplexer to be selected at the same time in what is referred to as multiplexer contention. If the selected inputs are of different logical values, this contention may result in high power consumption and damage to the circuit. The invention prevents the adverse consequences of multiplexer contention by disabling one direction of the driving capability for each driving gate in the multiplexer during a scan. Thus, the multiplexer output can be driven to only one logical value regardless of the logical values of the selected inputs. A controllable impedance element, such as a transistor, is coupled between an input driving gate of a multiplexer circuit and a voltage supply node. The impedance element is responsive to a scan control signal, such that the impedance element is disabled, i.e., at high impedance, during a scan procedure.

Abstract: A central processing unit is connected to an external memory including system memory and an external cache. The central processing unit includes a First-In-First-Out (FIFO) load buffer configured to generate an access to the external memory in response to a data prefetch command. The access to external memory has an associated data load latency period as data is moved from the system memory into the external cache. Instead of requiring the access to external memory to be completed before another FIFO load buffer address is processed, as is typically required in a FIFO load buffer configuration, the FIFO load buffer responds to the data prefetch command by processing additional stored addresses during the data load latency period.

Abstract: A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Abstract: A system for convening between parallel data and serial data is described. In the system (b 10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is convened into serial data.

Abstract: A microprocessor in a computer system processes an instruction stream comprising instructions of a plurality of instruction types including an information retrieval instruction type. The microprocessor comprises a register set, a pending fault flag set, a functional unit, an information retrieval subsystem, and a control subsystem. The register set comprises a plurality of registers, each register for storing information. The pending fault flag set comprises a plurality of pending fault flags each associated with one of said registers, each pending fault flag having selected conditions including a pending fault condition and a no pending fault condition. The functional unit performs processing operations in response to information input thereto. The information retrieval subsystem initiates an information retrieval operation to retrieve of information from said information storage subsystem for storage in a register.

Abstract: A method and apparatus for determining the size of a file cache for storing data is described. The method includes activating a filesystem logging mechanism to monitor filesystem transactions performed on the computer by the user. Next, a file cache is provided under computer control for storing at least a portion of at least one computer file. Also, a filesystem log file is provided for storing records of filesystem transactions invoked by the computer. A user work cycle is then performed during which the filesystem logging mechanism monitors filesystem transactions invoked by the computer and stores records of certain filesystem transactions to the filesystem log file. Finally, the size of the file cache required to store the information cached during the work cycle is determined by processing the log file. Also provided is a computer program product having computer readable code for determining the size of a file cache.

Abstract: An arbiter circuit is described that is capable of granting a first user access to a shared resource while concurrently arbitrating subsequent requests from the first user to other users seeking access to the shared resource. The arbiter of the present invention includes a first arbiter element and a second arbiter element. The first arbiter element is initially used to arbitrate and issue a grant signal in response to one or more request signals from two or more users. The second arbiter element arbitrates and issues the next grant signal in response to subsequent request signal or signals from the one or other users. In one embodiment of the invention, the first and second arbiter elements are used alternately. In other embodiments, third and fourth arbiter elements are used to arbitrate in response to subsequent requests. The arbiter circuits of the present invention all reduce the delays in the access of users to the shared resource.

Abstract: A distributed computer system has an information server and a plurality of client computers coupled by one or more communication paths to the information server. The information server includes a database management system (DBMS) with an interface procedure for receiving and responding to SQL statements from client computers. At least one client computer has a database access procedure for sending SQL statements to the DBMS in the information server. The database access procedure includes embedded encrypted SQL statements, representing a predefined subset of a predefined full set of SQL statements recognized as legal SQL statements by the DBMS. For instance, the predefined subset of SQL statement might include only SQL statements for reading data in the DBMS, but not include SQL statements for modifying and adding data to the DBMS. Each of the SQL statements sent by the database access procedure to the DBMS includes a corresponding one of the encrypted SQL statements.

Abstract: The disclosed method of designing a circuit includes the step of building a dependency graph for a set of computer program instructions. A set of artificial dependencies are inserted into the dependency graph to form a modified dependency graph. The artificial dependencies are hardware limitations such as register renaming limitations, branch prediction limitations, and memory disambiguation limitations. The execution performance of selected artificial dependencies of the modified dependency graph are then analyzed to generate a set of performance values. The top-ranked performance value is associated with a modified dependency graph with a selected set of hardware dependencies. A circuit specification corresponding to the modified dependency graph with the selected set of hardware dependencies is then used to fabricate a circuit.

Abstract: The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e.

Abstract: A method of locating a socket on a printed circuit board which includes the steps of fabricating a plurality of pads and one or more fiducials on the upper surface of the printed circuit board, optically aligning a drill with the fiducial, and then drilling a socket hole through the printed circuit board at the location defined by the fiducial. A peg of the socket is inserted into the socket hole to align the socket with the printed circuit board. Alternatively, a method for locating holes on a printed circuit board includes the steps of forming a master tooling hole through the printed circuit board, locating a fiducial on the printed circuit board using the master tooling hole as a guide, focusing on the fiducial with an optically alignable drill, thereby aligning the drill, and then drilling a hole through the printed circuit board using the aligned drill.

Abstract: The present invention provides a hybrid Non-Uniform Memory Architecture (NUMA) and Cache-Only Memory Architecture (COMA) caching architecture together with a cache-coherent protocol for a computer system having a plurality of sub-systems coupled to each other via a system interconnect. In one implementation, each sub-system includes at least one processor, a page-oriented COMA cache and a line-oriented hybrid NUMA/COMA cache. Such a hybrid system provides flexibility and efficiency in caching both large and small, and/or sparse and packed data structures. Each sub-system is able to independently store data in COMA mode or in NUMA mode. When caching in COMA mode, a sub-system allocates a page of memory space and then stores the data within the allocated page in its COMA cache. Depending on the implementation, while caching in COMA mode, the sub-system may also store the same data in its hybrid cache for faster access.

Abstract: A computer implemented method captures advertiser information received from an audio or video signal. The method includes the steps of receiving an incoming video or audio signal, determining whether the incoming video or audio signal includes advertisement specific data of an advertiser, and capturing and storing the advertiser specific data. The method also includes the steps of selectively performing, responsive to the request of a user, at least one of the following steps: printing the advertiser specific data including current and previous advertiser specific data upon request; displaying the advertiser specific data including current and previous advertiser specific data upon request; obtaining an advertiser destination number from the advertiser specific data and automatically attempting to establish voice connection with the advertiser upon request; providing directions to an advertiser location; and determining a geographically preferred advertiser.

Abstract: A system and method automatically configures protocol layer parameters in terminal and carrier equipment. The system includes a terminal equipment having an automatic configuration program. The automatic configuration program controls the operation of the terminal equipment and sends a series of probe to the carrier equipment. Each probe is constructed to test a specific parameter value, and to restrict a set of potential values for the parameter. The automatic configuration program receives answers back from the carrier equipment, which may accept or reject, or not respond to the probe. Based on the the probe, any previous probes, the answer, any previous answers, and the set of values for the parameter, the automatic configuration program constructs another probe in accordance with another value of the parameter. This other value is determined by restricting the set of potential values that may be used to configure the parameter.