Abstract: A method and apparatus for maintaining cache coherency in a multiprocessor system having a plurality of processors and a shared main memory. Each of the plurality of processors is coupled to at least one cache unit and a store buffer. The method comprises the steps of writing by a first cache unit to its first store buffer a dirty line when the first cache unit experiences a cache miss; gaining control of the bus by the first cache unit; reading a new line from the share main memory by the first cache unit through the bus; writing the dirty line to the shared main memory if the bus is available to the first cache unit and if not available, the first cache unit checking snooping by a second cache unit from a second processor; comparing an address from the second cache unit with the tag of the dirty line, wherein the tag is stored in content-addressable memory coupled to the store buffer and if there is a hit, then supplying the dirty line to the second cache unit for updating.

Abstract: A system and method for managing the distribution of licensed application programs stored on a server over a distributed computer system maintains control over the program even after the program has been distributed to a client computer from a provider on an information server. Protection may include license expiration date verification, authorized user ID verification, and protection against decompilation and reverse engineering by maintaining the program in an encrypted form until verification of the expiration date and user identity are complete and the program is ready for decoding, loading into the client computer CPU, and execution. A user identifies a program for trial use by any conventional means such as by using a network browser on the World Wide Web. The server recognizes a user request to access the application program. The server may have an agent on the client computer for performing certain predetermined administrative tasks.

Abstract: A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Abstract: An edge of a long PCI card plugs into a connector at one end of a computer enclosure. The opposite end extends into the enclosure and may be superimposed over a component such as a disk drive. The support of the present invention is rigidly mounted on the enclosure to fit under the inner end of the card. A slide on the support grips the inner end of the card. The slide is adjustably positioned on the support to accommodate cards of different lengths.

Abstract: In a computer system having a data processing unit, memory, and a multitasking operating system that supports multiple threads of execution in a shared address space, a resource allocation subsystem includes an initialization procedure for initializing monitors, a notify procedure and a wait procedure. Each monitor has an associated event data structure denoting the status of the monitor as Signaled or Unsignaled. Each monitor also stores a waiters value indicating how many threads are waiting on the monitor, a tickets value indicating how many of the threads are to receive notifications, and an epoch counter value. The notify procedure updates any specified monitor to the Signaled status, updates the specified monitor's tickets value to indicate how many waiting threads are to receive notifications, and updates the epoch counter to indicate an epoch value associated with the updating of the specified monitor's status to Signaled.

Abstract: A portfolio management system (PMS) is disclosed that allows users to manage, create, edit, debug and compile software portfolios that can include several different types of components, or projects. For example, projects can be Java applets, standalone executable programs, image files, Java class libraries or remote Java applets. The software portfolios and/or their constituent projects can be stored on the system hosting the portfolio management system or on any remote system that can be accessed via the Internet using standard Internet communications protocols, such as FTP or HTTP. The PMS includes portfolio files, each of which includes links to the projects that compose a portfolio and project files that set out the attributes of one project. The PMS also provides portfolio methods that allow users to create, choose, import and remove entire portfolios and project methods that allow users to create, import, choose, edit, remove, run, copy and paste projects.

Abstract: A multi-processor computer system is disclosed that reduces the occurrences of invalidate and copyback operations through a memory interconnect by disabling a first write optimization of a cache coherency protocol for data that is not likely to be written by a requesting processor. Such data include read-only code segments. The code segments, including instructions and data, are shared among the multiple processors. The requesting processor generates a Read to Share Always request upon a cache miss of a read-only datablock, and generates a Read to Share request otherwise. The Read to Share Always request results in the datablock stored in cache memory being labeled as in a "shared" state, while the Read to Share request results in the datablock being labeled as in an "exclusive" state.

Abstract: A phase detection circuit detects a phase relationship between a first clock signal, characterized by transitions of a given polarity (e.g., rising edges) at a first frequency, and a second clock signal, characterized by transitions of the given polarity at a second frequency that is an integer multiple of the first frequency. Transition indication circuitry generates a transition indication signal responsive to transitions, of the given polarity, of the second clock signal. The transition indication signal includes a transition indication (e.g., a pulse) corresponding to each n.sup.th transition, of the given polarity, of the second clock signal and at a phase that is selectable relative to the first clock signal in response to a transition indication control signal. Sampling circuitry (e.g., one or more latches) samples the transition indication signal responsive to each transition, of the given polarity, of the first clock signal to generate a transition indication sample.

Abstract: An aircraft N-number control system includes a receiver for receiving aircraft identification information signals representing alphanumeric characters corresponding to an aircraft. A microprocessor operating in accordance with stored programming instructions processes the received aircraft identification information signals into alphanumeric codes, determines whether there is a substantial similarity between the alphanumeric codes representing two aircraft and generates an output signal representing the alphanumeric codes only if there is no substantial similarity. The alphanumeric codes representing the aircraft are displayed on a air traffic controller's radar screen in response to the output signal.

Abstract: An apparatus for use in testing wire bond or flip chip connected integrated circuits includes a housing with a top side, a bottom side, and a perimeter region defining a housing central aperture. The housing further includes flip chip pads to accommodate flip chip solder connections to a flip chip integrated circuit during a first test period and wire bond pads to accommodate wire bond connections to a wire bond integrated circuit during a second test period. There are connector pins on the bottom side of the housing for connection with a printed circuit board. The printed circuit board includes an access aperture which is aligned with the housing central aperture. This configuration allows a test probe to access a flip chip integrated circuit positioned within the housing. It also allows a heat sink to be used when the housing incorporates a wire bonded integrated circuit.

Abstract: In summary, the present invention is a multithreaded computer system having a memory that stores a plurality of objects and a plurality of procedures. Each object has a lock status of locked or unlocked, and includes a data pointer to a data structure. The system uses a first object locking procedure to service lock requests on objects that have never been locked as well as object that have not recently been locked, and uses a second object locking procedure to service lock requests on locked objects and object that have been recently locked. The first object locking procedure has instructions for changing a specified unlocked object's lock status to locked, for copying the data structure referenced by the data pointer to an enlarged data structure including a lock data subarray for storing lock data, and for updating the data pointer to point to the enlarged data structure. The second object locking procedure has instructions for updating a specified object's stored lock data.

Abstract: A method and apparatus for compiling a source program to yield an object program. A syntactical analyzer stores pointers into an ID table into a parse tree instead of storing identifier names in the parse tree. The ID table has a Current Effective Definition (CED) for each identifier that changes as various blocks of the source program are entered and exited. The CED always points to a location in the symbol table where information about the current definition of the identifier is stored. A syntactical analyzer in the compiler uses the information stored in the parse tree to avoid searching the symbol table.

Abstract: A multi-threaded processing system has a cache that is commonly accessible to each thread. The cache has a plurality of entries for storing items, each entry being identified by an entry number. The location in the cache of an item that includes a first key is determined by supplying the first key to a lockless-lookup engine which then provides a lookup output that is alternatively a lookup entry number or an indication that the item is not stored in the cache. The lookup entry number is alternatively a first or second entry number, wherein the first entry number points to a first entry in which the item is stored and the second entry number points to a second entry in which the item is not stored. If the lookup output is the lookup entry number, then it is verified that the lookup entry number is the first entry number.

Abstract: Handle-based finding operations for search operations in an operating system in a computing system are converted into non-handle-based finding operations. The invention is responsive to a program module performing search operations specifying a file search path and has a find first module, a find next module and a find close module. The find first module, in response to a find first call from the program module, locates a search block for use in storing file identification information for a first file in the file search path. The find first module marks the search block as "in use," generates a handle identifying the search block and passes the handle back to the program module. The find next module is responsive to a find next call containing the handle. The find next module converts the handle into a search block address and locates the search block from the search block address. The search block is used to store the file identification information for a next file in the file search path.

Abstract: A device driver interface for achieving portability of device drivers for operating with full source level compatibility across multiple instruction set architectures and platforms. The device driver interface makes transparent to the driver the actual data access mechanisms of the host computers on which the driver is compiled.

Abstract: A method and apparatus for generating more helpful error messages during compilation of a software program. The software program contains a macro definition and an invocation of the macro. The macro is expanded during the compilation process. The invention generates several tables that save the history of the macro expansion. If an error occurs during compilation of the macro, the invention prints an error message, using the saved history information, that specifically identifies the location of the error in the source program of the macro and the history of the macro expansion. The invention can print multi-line macro histories for nested macro calls.

Abstract: A database management system (DBMS) benchmark testing system for testing performance of a plurality of DBMS's stores both DBMS independent and DBMS specific files in a computer memory. The DBMS specific files include performance statistics collection procedures for each said DBMS, procedures for performing various DBMS operations for each DBMS, and environmental parameter definition files for each DBMS for specifying DBMS environmental parameters that control the configuration and operation of each DBMS. DBMS independent test scripts specify operations to be performed by specified ones of the DBMS's so as to test performance of the DBMS's, and specify performance statistics to be collected by the performance statistics collection procedures while the DBMS performs the specified operations.

Abstract: A device for receiving thermal conduit comprising a thermally conductive material for coupling between an end of a conducting element of the thermal conduit and an end of an outer shell of the thermal conduit. The thermally conductive material is arranged to physically define a best thermal path from the end of the conducting element to the end of the outer shell such that substantially all thermal energy dissipated from the conducting element to the outer shell flows along the best thermal path. The length of the best thermal path is significantly greater than a nearest distance between the conducting element and the outer shell, and the conductive material is thin and manufactured of a poor thermal conductor such that the total energy dissipated along the best thermal path is reduced.