Abstract: A computer network having first and second network entities. The first network entity includes a packet object generator that generates a packet object including an executable source method, an executable destination method, and data associated with each of the methods. The first network entity also includes a communications interface to transmit the packet object. The second network entity includes a communications interface to receive the packet object and an incoming packet object handler to handle the received packet object. The incoming packet object handler includes a source and destination verifier to execute the source and destination methods with their associated data so as to verify the source and destination of the received object packet.

Abstract: A card guide that both restrains an installed electronic card and allows the card to be inserted into a computer chassis in a direction that is parallel to the motherboard of the computer. The card guide extends from a beam that is cantilevered from a frame of a computer chassis. The card guide has a groove that guides an edge of the electronic card so that the card is aligned with a connector of the motherboard. The card guide also has a ramp that guides the card into the groove in a direction parallel with the motherboard and perpendicular to the groove. The card is installed by initially pushing the electronic card along the ramp until the edge of the card snaps into the groove. The cantilevered beam is deflected by the installation force of the user to allow the card to move down the ramp. Once in the groove the electronic card is pushed in a direction perpendicular to the motherboard to plug the card into the motherboard connector.

Abstract: A network interface card (NIC) is provided with a transmit unload block for asynchronously segmenting packet data into ATM cells for packets of multiple channels. The transmit unload block comprises a cellification block and a cellification and DMA scheduler. The cellification block is used to perform the actual cellification of the packet data into ATM cells, one ATM cell at a time, and management of the packet control data associated with the ATM cell's packet as well as management of the buffer control data associated with the ATM cell's channel. The construction of the current ATM cell is overlapped with the management of the packet and buffer control data associated with the immediately preceding ATM cell. The cellification and DMA scheduler is used to control the operation of the cellification block. The cellification and DMA scheduler is also used to schedule DMAs to obtain additional packet data for the channels.

Abstract: An electronic device and method for utilizing two extra microcode instructions to generate a set of test patterns which provide complete bitwise self-testing of the on-chip memory of a microcode sequencer. The self-testing sequence can be triggered by a single external interface event.

Abstract: The present invention provides an economical, high performance, adaptable system and method for a type-specific data presentation by a development tool. In the preferred embodiment, one or more type-specific function name are found from the symbol table of the target program which might be able to display a data object. These type-specific function names are analyzed to determine if one and only one such name is able to display the data object and if so the found function name is used to call that function to display the data object. In the preferred embodiment the development tool is a debugger for C++ target programs.

Abstract: The system of the present invention includes programmable logic to generate watchpoint traps which cause a branch to determined trap code and breakpoint signals which cause the stopping of the system dock. Furthermore, the system can measure system performance criteria. The logic is flexible and easy to program, but sophisticated in application to provide a variety of criteria that trigger on events which in turn increment the counters. In the preferred embodiment, the system includes two counters and trigger decode logic to increment the counters. Each counter is independently programmable to enable the user to determine such performance information as average latency, which is a combination of one counter counting the number of occurrences of a particular event and a second counter counting the duration of the events. Both counters can be programmed to measure on edges or levels of signals.

Abstract: A low-loss, low-inductance metal interconnect for an electrical signal in a microcircuit comprises a plurality of spaced-apart generally parallel metal interconnect lines disposed in a plane over an insulating layer. The metal interconnect lines are interleaved with and electrically insulated from a plurality of spaced-apart generally parallel metal lines disposed in the plane. The metal interconnect lines together comprise a signal interconnect path, and the metal lines are coupled to a fixed voltage potential, such as ground.

Abstract: Software systems such as file systems in a computer are tested by scatter load testing. Scatter load testing is accomplished by the computer system applying randomly selected operative test situations to the software system. The operative test situations are randomized by the computer randomly selecting a geometry, or configuration, for the software system under test and randomly selecting a workload on the selected software system configuration. The randomization of workload selection can be further enhanced by expanding the workload to one or more tasks and randomly selecting objects, actions and parameters that make up each workload task to be performed during the test. As the random operative situation is run on the system, operation test results are output from the computer to indicate the performance of the software system being tested. Choice constraints may be placed on the random selection of the various test elements of the operative test situation.

Abstract: A method for identifying false paths in a digital circuit. A list of paths corresponding to the digital circuit is either provided or generated. For each path, an AND gate is created. For each element in the path, the off-path signals of the monitor circuits corresponding to the elements of the path are coupled to the input of the AND gate. A plurality of different signals are input to the digital circuit in an attempt to generate a "1" at the output of the AND gate. A false timing path signal is generated for that path if the AND gate does not output a "1" within a pre-determined amount of time. This process is repeated for each path of the digital circuit to identify all false timing paths.

Abstract: A computing system operates a volume management system to manage accesses to the storage of information and provides to the users of the volume management system parallel process paths for accessing a storage device is as an access volume operation or as an access device operation. Further the volume management system prevents the two parallel logical operations from conflicting with each other by performing an open volume operation and an open device operation. These operations indirectly communicate by setting and clearing characteristics in stored volume data characteristics that they share for each device being accessed. The characteristics include an open count to track the open status of a device and an exclusive flag to track whether the storage device has been opened exclusively by either the open volume or the open device operation request from a user.

Abstract: A memory array with improved access time is disclosed. In one embodiment, the memory array includes a plurality of memory cells arranged in rows and columns. Each one of the plurality of columns includes a global bit line, a local bit line with a memory cell coupled thereto, and an MOS switch configured to selectively couple the local bit line and the global bit line in response to a column select signal. In a second embodiment, the memory array includes a plurality of sense amplifiers located at the periphery of the array, and a plurality of columns associated with the plurality of sense amplifiers respectively. Each one of the plurality of columns includes a global bit line, a local bit line with a memory cell coupled thereto; and a switch coupled between the local bit line and the global bit line and configured to selectively move the global bit line in response to the contents of the memory cell during a read operation.

Abstract: Two independently accessible subdivided cache tag arrays and a cache control logic is provided to a set associative cache system. Each tag entry is stored in two subdivided cache tag arrays, a physical and a set tag array such that each physical tag array entry has a corresponding set tag array entry. Each physical tag array entry stores the tag addresses and control bits for a set of cache lines. The control bits comprise at least one validity bit indicating whether the data stored in the corresponding cache line is valid. Each set tag array entry stores the descriptive bits for a set of cache lines which consists of the most recently used (MRU) field identifying the most recently used cache lines of the cache set. Each subdivided tag array is provided with its own interface to enable each array to be accessed concurrently but independently by the cache control logic which performs read and write operations against the cache.

Abstract: A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Abstract: This Continuation-In-Part describes a part of this run-time debugger operation which is designated the "Fix-and-Continue" invention. This invention permits a user to begin a debugging session wherein if an error in the code is encountered, the user can edit the corresponding source code to correct the error and then execute a "Fix and Continue" command all without leaving the debugging session. The Fix and Continue code calls the compiler to recompile the source code file with the edited text in it, receives the resulting recompiled object code file from the compiler, uses the dynamic linker to link the recompiled object code into the target application program process, patches the previous version of this same object code fie to refer to the newly recompiled code, resets any required variables and registers, resets the program counter to the line of code being executed when the error was discovered.

Abstract: A method and apparatus of coordinating data transfer between hardware and software in a computer system through the use of a semaphore mechanism is disclosed. When a data packet is queued by preparing an entry in a data descriptor ring, software provides the descriptor entry number to a first storage field in a predetermined storage location which is accessible by hardware. Hardware accounts for the transactions it has completed by writing the descriptor entry number to a second storage field in the storage location. To determine if there is additional data to process, hardware compares the contents of the first storage field and the contents of the second storage field. If the contents of both storage fields are equal, the corresponding ring or channel has run out of data and no additional data is to be processed.

Abstract: A method and an apparatus for verifying a network transporter under test which is able to perform the test and produce test results by posting test packets through network transporter without requiring large amounts of memory and producing results in a short period of time. The present invention utilizes one or more FIFO (First In First Out) buffers in which plurality of components of each packet is stored just as each packet is posted to the network transporter under test. As soon as the corresponding packet is received on the other side of the network transporter, plurality of components and the receive packet are compared and a test result is produced. As soon as such comparison is performed and completed and the test results are produced, the corresponding plurality of components stored in the FIFO is discarded and the corresponding memory space used is freed up for the next packet's test information.

Abstract: A video adapter and computer/video system generate a video output signal having a first format useable by other video equipment. This signal is then looped back through the video adapter to generate a signal in a second format suitable for previewing on a monitor or display. The video adapter includes at least first and second data rate changers (preferably FIFOs), a controller unit, and circuitry for scaling and color-space converting the computer-processed video into the second format. Externally provided video input is multiplexed to a rate-increasing FIFO whose output is coupled to an IOSIMM unit in the computer/video system for video processing, through a master rate-decreasing FIFO whose output is output-controlled, format-processed and provided as the first format output signal. The output-controlled signal is coupled to a scaler, color-space converter and passed to a master rate-increasing FIFO.

Abstract: Computers are manufactured with connectors in which are inserted at least one PCI expansion card to increase the capacity of the computer. A computer enclosure panel is formed with first opening for insertion and withdrawal of the card. The card has a cover which blocks the first opening after the card has been plugged in. The invention provides a retainer mounted on the rear panel which engages the cover to hold one end of the card in place. The invention further provides room for the tab conventionally extending outward of the card to extend outward of the enclosure so that the card may be located closer to the side panel, thereby conserving space within the enclosure. The retainer has an apertured first door pivotally mounted on the exterior of the panel which in closed position surrounds a second opening through which the card tab protrudes and engages one face of the tab. A second door is pivotally mounted on the first door and in closed position covers the aperture in the first door.

Abstract: A method and an apparatus for a dynamic error injection mechanism used in conjunction with a behavioral simulator in testing simulated hardware and software, and more particularly the testing of error handling code. In one implementation of the invention, Sun Microsystem's MPSAS (MULTI-PROCESSOR SPARC ARCHITECTURAL SIMULATOR) may be utilized as a behavioral model to implement the present invention. With the present invention, a range of addresses may be specified within which to test such errors. When such a command is issued, MPSAS logs the error and address range. Simulation can then be continued. At the next access to the address range to be tested with for a specific error, the present invention triggers off simulated hardware actions which would be taken in an actual hardware upon its encountering the same error. If the corresponding error handlers are turned on by the software of the present invention, the trap will be taken and the code will vector off to the error handler.