Abstract: An insert is installed at a corner and two adjacent edges of an enclosure for electronic equipment so that a signal light, such as an LED, may be observed from two sides of the enclosure. The insert has a prism to refract light in both directions from an LED or similar signal light supported on the insert in a fixed position relative to the prism. The corner of the prism is rounded to function as a lens. The corner of the enclosure is cut away at the upper edges of the converging sides and the cut-away area filled with the lens. An apron depending from the insert may be welded or otherwise adhered to the interior of the enclosure.

Abstract: A method and apparatus for simulation of a hardware design using a cycle-based event-driven simulation. The present invention also provides for a measuring technique for estimating the potential performance gain obtained by using traditional simulation techniques as opposed to the cycle-based event-driven simulation technique of the present invention. The result of the measuring technique is provided for a user as a tool in determining which technique they would like to use for the simulation of their hardware design.

Abstract: In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8 implementation cascades three partial remainder computation circuits and overlaps three quotient selection circuits. Two carry save adders speculatively compute the possible resulting partial remainders corresponding to each possible value, -1, 0 , and +1, of the quotient digit by adding the divisor, not adding anything, and adding the two's complement of the divisor, respectively, thus shortening the critical path of a single SRT iteration producing a single quotient digit. The propagation delays of two carry save adders which speculatively compute the possible resulting partial remainders are masked by a longer delay through quotient selection logic.

Abstract: The state of a functioning computer operating system is quickly stored onto a nonvolatile storage device such that the computer system may be suspended quickly. To quickly save the state of computer operating system, a process firsts prepares for the computer system suspend by allocating a file on the root file system that will store operating system state data. The process then warns each user application process running on the computer system to allow each user application process to prepare for the suspend. After the warning, the process suspends each user application process. The memory space used by each user application process is then swapped out to nonvolatile storage. Next, the various kernel daemons and operating system subsystems are suspended. Finally the process suspends the device drivers running on the computer system such that there is no activity in the computer system. A compressed version of the operating system state is then written to a nonvolatile storage device.

Abstract: A method and for multiplexing pixel data from a frame buffer to a RAMDAC to reduce the number of pins required. For many graphics operations optimal performance is achieved by storing an entire 32-bit pixel in a single RAM chip. When displaying video data from a frame buffer, pixels must be read out serially from the frame buffer at real-time speeds. A frame buffer memory with 16 pins for serial video output is used. An entire 32-bit pixel is stored in a single RAM chip. For a 32-bit pixel containing four byte (8-bit) quantities designated X, B, G and R, on the first clock cycle, the X and B bytes are made available on the 16 pins of the frame buffer. On the next clock cycle, the G and R bytes are made available. Thus, over two cycles the entire 32-bit pixel is output from the frame buffer to a RAMDAC which samples the X and B bytes on 16 input pins. The RAMDAC stores these X and B bytes in an internal register. On the next clock cycle it samples the G and R bytes.

Abstract: A computer memory system and method utilizes a disk drive as a caching device to overcome the size and cost limitations of conventional semiconductor cache memory. Despite providing somewhat slower access times than semiconductor cache memory, utilizing one or more disk drives as a caching device allows enhanced performance to be maintained for longer times under sustained loads by effectively decreasing the latency of the primary storage device, combining relatively small random requests into larger sequential requests, balancing the input/output ("I/O") load over several disk devices and/or canceling duplicate writes.

Abstract: A system and method for a simultaneous multi-band block-stop filter is disclosed. The block-stop filter provides rapid filtering of an input data stream by simultaneously comparing a plurality of data band components to the low threshold, associated with the band of which the particular data band component is a member, and then simultaneously comparing the plurality of data band components to an associated high threshold. The block-stop filter can also improve performance by parallelizing the act of storing the filtered data band components into the output data stream.

Abstract: A computer system includes a program executer that executes verifiable architecture neutral programs and a class loader that prohibits the loading and execution of non-verifiable programs unless (A) the non-verifiable program resides in a trusted repository of such programs, or (B) the non-verifiable program is indirectly verifiable by way of a digital signature on the non-verifiable program that proves the program was produced by a trusted source. In the preferred embodiment, verifiable architecture neutral programs are Java bytecode programs whose integrity is verified using a Java bytecode program verifier. The non-verifiable programs are generally architecture specific compiled programs generated with the assistance of a compiler. Each architecture specific program typically includes two signatures, including one by the compiling party and one by the compiler. Each digital signature includes a signing party identifier and an encrypted message.

Abstract: A number of methods and apparatus are disclosed for providing transparent persistence in a distributed object operating environment are disclosed. In general, the present invention teaches replacing the value in the object's data pointer (addressing information which points to the objects limited persistent memory) with a pointer value which points out to another persistent storage device. In preferred embodiments, a persistent storage manager (external and transparent to the distributed object) maintains the object data. In a specific embodiment, a distributed object framework is provided which has the mechanism for providing the transparent persistent strategy of the present invention. An object developer develops object implementations which the distributed object generates distributed objects with, in the process automatically providing transparent persistence.

Abstract: A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independently initiating a transition into a power-conserving mode, i.e., a "sleep" state, while keeping its network interface "alive" and fully operational. Subsequently, each computer system can independently transition back into fully operational state, i.e., an "awake" state, when triggered by either a deterministic or an asynchronous event. As a result, the sleep states of the computer systems are transparent to the computer network. Deterministic events are events triggered internally by a computer system, e.g., an internal timer waking the computer system up at midnight to perform housekeeping chores such as daily tape backups.

Abstract: A circuit and method for optimizing efficiency in transferring a block of data having a plurality of frames of limited size from a memory element. The circuit comprises a transmit ("TX") DMA engine and a TX Segmentation engine. The TX DMA engine is responsible for accessing overhead information for the block of data within a TX data buffer from a data descriptor dedicated to that particular TX data buffer. The TX DMA engine is further responsible for reading the block of data from the memory element to be stored local thereto. The TX Segmentation engine is responsible for segmenting the block of data into a plurality of cell packets corresponding in number to the plurality of frames. Each cell packet contains in common the overhead information for the block of data to avoid the TX DMA engine re-accessing the data descriptor to obtain the same overhead information for each frame being transferred.

Abstract: An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers.

Abstract: A computer has an AC power outlet, preferably a standard AC outlet, into which periperhal devices, such as video monitors, can be plugged. It can turn this outlet on and off under program control, preferably by writing an outlet control signal to an I/O port which controls the outlet. A activity monitor, preferably in software, generates outlet control signals when one or more of the computer's peripheral devices have been inactive for more than a predetermined time. In some embodiments, the activity monitor turn off different parts of the computer in response to different types of inactivity. Preferably the computer can turn off the AC outlet without turning off the computer as a whole, and preferably it turns off the AC power outlet when the computer is turned off. Normally the AC outlet and its switching circuitry are part of the computer's power supply.

Abstract: The present invention operates within a data processing system including a processor coupled to a memory controller unit which is coupled to memory used for storing and retrieving data. The memory controller unit provides separate read and write data pipelines, allowing write operations to overlap preceding read operations. The present invention selectively delays a certain limited number of write operations, delaying a write operation only if it is directed to the same memory address as that of a preceding read operation. By delaying this limited number of write operations, the present invention substantially preserves the advantages of write overlap while preventing the problem of overwrite. An alternative embodiment of the present invention selectively suppresses error writeback operations associated with a read operation if the read operation is followed by a write operation to the same address.

Abstract: In a communication network having a set of hosts and switch based label swapping communication nodes, each node has a control processor that is also a host that sends and receives messages via the switching apparatus in its associated node. At least one of the hosts includes a distribution tree set up procedure. That procedure stores source and destination data designating a set of source hosts and a set of destination hosts in the communication network, and defines a distribution tree of virtual connections. The designated source hosts and destination hosts may include the control processors of some or all the network nodes. The defined virtual connections include a virtual connection from each designated source host to all of the designated destination hosts, and message labels for all messages sent by the source hosts to be routed to the destination nodes.

Abstract: A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller. The system controller processes each memory transaction and maintains a set of duplicate cache tags (Dtags) for each data processor. Finally, the system controller contains transaction execution circuitry for activating a transaction for servicing by the interconnect.

Abstract: A simulator is described in which the simulator can flashback to simulate events that in simulated time actually occurred earlier than other events already simulated. The simulator removes the restriction of a monotonic relationship between simulation time and simulated time, enabling improved simulator performance.

Abstract: A counterflow pipeline having a scoreboard table and a register file is disclosed. In the counterflow pipeline, information flows in two directions. Instructions flow up the pipeline during execution. The results from previous instructions flow down the same pipeline. As an instruction meets a result that is needed by that instruction, that result is garnered. The scoreboard table maintains a record of the registers values that are being recomputed in the counterflow pipeline at any given point in time. When a new instruction enters the counterflow pipeline, the register values it needs are compared to the record of register values being recomputed or otherwise stored in the scoreboard table. If a match occurs, the source value is not fetched from the register file. Rather, the needed source value is garnered in the counter flow pipeline. By this procedure, the number of times the register file need be accessed is significantly reduced.

Abstract: High speed shifting of test data through an integrated circuit is achieved by modifying the output portion of a circuit, while still observing relevant test standard protocols, such as the Joint Test Access Group, IEEE Std. 1149.1, entitled IEEE Standard Test Access Port and Boundary-Scan architecture. An output signal generated during a first signal transition of a first clock cycle is passed through a large output multiplexer with a long path delay. A cycle-insertion switching element is connected to the output node of the output multiplexer. The cycle-insertion switching element generates an output signal in response to a first signal transition of a second clock cycle. An output switching element applies the output signal to an output pin in response to a second signal transition of the second clock cycle. A second multiplexer is used to select the output signal from either the output multiplexer or the cycle-insertion switching element.