Abstract: A floating point mantissa final addition and rounding unit uses a conditional sum adder to reduce a redundant carry-save format 106-bit mantissa to a non-redundant properly rounded 53-bit double-precision mantissa. The conditional sum adder simultaneously speculatively computes both the sum and the incremented sum of the upper 52 bits of the carry-save portions. A rounding unit speculatively computes the lower one bit and two bits of the mantissa for the cases of mantissa overflow or non-overflow, respectively. The rounding unit produces an overflow carry signal and a non-overflow carry signal. A multiplexor selects the proper 53 mantissa output bits from among the two conditional sum adder outputs and the rounding unit mantissa outputs depending upon the most significant bits of the two conditional sum adder outputs and the overflow and non-overflow carry signals.

Abstract: A CMOS regulated complementary charge pump circuit uses imbalanced current regulation and symmetrical capacitive loading of input signals to provide a proportional response and high sensitivity at small phase differences. The charge pump is suitable for operation at very high frequencies, and therefore finds applications in delay-locked and phase-locked loops used to regenerate system clock signals within VLSI circuits. The use of current limiting devices in the switch pass gates permits a balancing of the capacitive loads presented to the input signals. Adjustable capacitors permit the elimination of a static phase offset at a zero operating point.

Abstract: A flip-flop with scan capability includes a four switches, a master stage, a slave stage and a scan-out logic gate. The flip-flop can operate in a functional mode, and a scan mode and receives a clock signal, a data signal, a scan clock signal and a scan-in signal. The flip-flop enters the functional mode when the clock signal runs free and the scan clock signal is held constant. The first switch receives the data signal and provides the data signal to the master stage for storage during a first part of a clock cycle. During a second part of the clock cycle, the third switch, connected between the master stage and the slave stage, closes, providing the data stored in the master stage to the slave stage and outputted as a q output signal. The flip-flop enters the scan mode when the clock signal is held constant and the scan clock signal runs free. The first switch is controlled to stay open by the constant clock signal.

Abstract: The present invention provides a verifier for use in conjunction with programs utilizing data type specific bytecodes for verifying the proper operation of the executable program prior to actual execution by a host processor. A verifier is provided which includes a virtual stack for temporarily storing stack information which parallels the typical stack operations required during the execution a bytecode program. The verifier also includes a stack snapshot storage structure having a snapshot directory and stack snapshot storage area for storing the state of the virtual stack at various points during program verification so as to assure proper stack manipulations by the source program. A two step source program verification process is provided for in which the source program is initially loaded into the verifier and a first pass source program evaluation is performed.

Abstract: A method and apparatus for generating additional implicit keys from a key [K.sub.ij ].sub.N without the necessity of generating a new Diffie-Helman (DH) certificate or requiring communication between nodes to change implicit master keys is disclosed. A first data processing device (node I) is coupled to a private network which is in turn coupled to the Internet. A second data processing device (node J) is coupled to the same, or to a different network, which is also coupled to the Internet, such that node I communicates with node J using the Internet protocol. Node I is provided with a secret value i and a public value. Data packets (referred to as "datagrams") are encrypted to enhance network security. Each node maintains an internal value of N which is incremented based on time and upon the receipt of a data packet from another node. The key [K.sub.ij ].sub.N.sbsb.i is derived from the appropriate quantity of .alpha..sup.Nij by using high order key-sized bits of the respective quantity.

Abstract: A new register test system and method is provided for testing a register. The register under test has a number of bit storage locations, each of which is associated with one of a plurality of categories, including, for example, a read/write category, a read-only category, a write-only category, an always-"1" category and an always-"0" category. In accordance with the method, in each of a plurality of iterations, a data word is generated, stored it in the register under test, and thereafter retrieved from the register. For each iteration, an expected pattern is generated for comparison to the retrieved contents, using the original data, the retrieved contents and a plurality of mask patterns each associated with one of the categories. The expected pattern is compared to the pattern of the contents retrieved from the register and whether the register is deemed to be operating properly can be determined by whether the expected pattern corresponds to the retrieved pattern.

Abstract: A transmission data buffer and method for buffering data to be transmitted from a host computer to an asynchronous transfer mode (ATM) telecommunications network. The transmission data buffer comprises a plurality if FIFO memories, one for each channel which is established on the connection to the ATM network. A load engine loads packets of data (e.g. AAL5, AAL5-MPEG, TCP packets) into particular FIFO memories in the transmission buffer according to a load schedule queue. The data is removed from the FIFO memories by an unload engine according to entries in a bandwidth group table. The unload engine segments the data as it is removed from the FIFOs, by removing one ATM cell payload (48-bytes) at a time, and adds the ATM cell header data. The unload engine can also generate AAL5 packet CRC fields and add a control and length field to the cell data segmented from an AAL5 packet.

Abstract: The present invention provides a system and process which has the advantages of shortening the time and cost required to create a new localized version of a software product by automating much of the language translation process; by providing tools to automate the modifications to the program being localized, thereby reducing the probability of creating errors in the localization process and providing some measure of consistency between subsequently localized new releases of the product, and between different locales. The system disclosed includes an environment and tools to develop software modules to create methods to display, enter or print various single and multi-byte character sets. Moreover the system disclosed provides a mechanism for an independent software developer to localize a software product, using only a binary copy of the target program and the localization tool kit for that product.

Abstract: Apparatus and methods are disclosed for determining a load latency value to use in scheduling instructions for a target program, (the load latency value is the separation between a load command and the using instruction, wherein the expected return of the data is a function of where in the system the requested data resides). The instruction scheduling function is the modulo scheduling function of an optimizing compiler. Most modem microprocessors have the ability to issue multiple instructions in one clock cycle and/or possess multiple pipelined functional units and typically multi-level memory devices such as on-chip cache, off-chip cache as well as main memory. For such microprocessors this invention can, where applicable, accelerate the execution of modulo-scheduling loops in the target program code. The invention consists of a technique to determine an optimal load latency value given an rmii vector, which is a set of rmii values which correspond to different values of instruction load latency.

Abstract: A method and apparatus for reducing arbitration latency. A fast mode is defined to allow simultaneous request and access to a shared resource. A slow mode is defined to require a request, followed by arbitration, followed by access to the resource. By dynamically switching between fast and slow modes responsive to the volume of requests received, arbitration latency is reduced.

Abstract: A circuit and method for generating a checksum for a TCP packet on the fly. A stream of 32-bit data words from a TCP packet is split into two 16-bit data word streams and separately summed using 16-bit adders. The carry-out from the adders is tied to the carry-in thereof so as to incorporate any carry bits generated into the sum. At the end of the data stream, three further summing cycles are used in order to generate the final 16-bit one's complement checksum. First, the two 16-bit data stream partial sums are added together, including any carry bit from one of the adders while the carry-out from the other adder is stored. In the second cycle the stored carry-out and the carry-out from the first cycle are added into the sum. In the third cycle, any carry bit generated in the second cycle is added to the sum so as to produce the final checksum.

Abstract: An array of termination resistors has symmetrical geometry producing essentially no net magnetic field and a resultant low inductance is fabricated on a substrate as disk resistors. Conductive through vias are formed in the substrate in an array pattern defining what will be resistor first and second contacts. Each disk resistor has one first contact located at the resistor disk center, and preferably four second contacts located symmetrically about the resistor disk and shared by four adjacent disk resistors. For each resistor, a annular-shaped disk of resistive material is fabricated on a first surface of the substrate, such that a central opening in the disk overlies at least the upper surface of a first contact via. The disk geometry and material determines its resistance. Next, a layer of conductive material is formed over the first surface of the substrate to cover at least the periphery of each disk, and to fill the central opening in each disk.

Abstract: A sequential phase-frequency detector circuit using precharged logic and a minimum number of transistors is suitable for use in a delay locked loop because of insensitivity to a stuck delay line output signal. The detector receives standard REFERENCE and LOCAL input signals and provides UP and DOWN output signals for control of a charge pump. In one embodiment, the detector includes a pulse generator for isolating the reset of the UP output signal from a stuck delay line output. This feature permits the UP output to be turned ON while the LOCAL input is stuck at a high level. The circuit exhibits improved gain at phase differences of less than 20 pico-seconds, resulting in reduced phase jitter. The isolating feature minimizes frequency acquisition time in applications in which the frequency of the REFERENCE signal is sometimes substantially reduced, such as during an Energy-Star.TM. power-conserving or Slow modes, which typically causes the delay line output to become stuck.

Abstract: Interrupts are presented to a processor to indicate the arrival of data packets from a high speed network. The rate of packet arrival interrupts is modulated to prevent burdening the processor unnecessarily with repeated interrupts while receiving a burst of data. The interrupt modulator of the present invention ensures that the first packet of a new data burst, or the first packet of a short message, generate an immediate interrupt to the processor, thus avoiding any unnecessary latency in the processor's response. This is done by enabling a packet arrival to generate an interrupt if a specified period of time has elapsed since the previous interrupt. Further, the interrupt modulator ensures that every N'th packet that arrives generates an interrupt--for example, to ensure that the processor performs any memory management functions that may be required. A packet does not generate an interrupt if it arrives soon enough after the previous interrupt and it is not the N'th packet since the pervious interrupt.

Abstract: Electromagnetic interference ("EMI") generated by a flat panel video display system is reduced by periodically phase/modulating the panel clock. This spreads EMI energy associated with each panel clock harmonic by a frequency amount .DELTA.f proportional to the rate of phase change in the panel clock signal. EMI energy associated with each panel clock harmonic is reduced relative to a square-wave panel clock signal because the same energy is now spread over a group of frequencies centered about each harmonic. The phase of the panel clock is changed at a rate exceeding the bandwidth f.sub.m of a standard EMI measurement reference window. This disperses adjacent spectral energy sufficiently so the reference window measures but one, decreased, amplitude at a time. Phase-modulation may be achieved using a clock pulse dropping circuit that receives a square-wave input of frequency Nf.sub.

Abstract: Embodiments of the present invention use a new extension to the HTML language to support remotely specified named anchors. A remotely specified named anchor, when embedded within a source document, instructs a browser program to access a portion of a destination document indicated in the remotely specified named anchor. When the browser program reads a remotely specified named anchor such as<a href=http://foo.com/bar.html/SCROLL="Some Text">from the source document, the browser program performs the following steps: 1) the browser retrieves the destination file "bar.html" from the server "foo.com", 2) the browser searches the file bar.html for "Some Text", and 3) if the browser finds the character swing being searched for, then the browser displays the file bar.html, scrolled to the line containing the first character of the character string being searched for.