Abstract: An optimizing compiler process and apparatus is disclosed for more accurately and efficiently identifying live variable sets in a portion of a target computer program, so as to more efficiently allocate registers in a computer central processing unit. The process of the invention includes the steps of performing a static single assignment transform to a computer program, including the addition of phi functions to a control flow graph. Basic blocks representing a use of a variable are further added to the control flow graph between the phi functions and definitions of the variables converging at the phi functions. A backward dataflow analysis is then performed to identify the live variable sets. The variables in the argument of phi functions are not included as a use of those variables in this dataflow analysis. The dataflow analysis may be iteratively performed until the live variable sets remain constant between iterations.

Abstract: A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller and for receiving cache access requests from the system controller corresponding to memory transaction requests by other ones of the data processors.

Abstract: A mulitport register file including a memory cell array having a plurality of addressable memory locations and N bit lines associated with each memory cell in the memory cell array, wherein there are N port inputs to each addressable location in the memory cell array and at most N/2+1 word lines associated with each addressable memory location. A plurality of select and priority circuits having N port inputs and at most N/2+1 outputs, the outputs of a separate select and priority circuit connected to the word lines associated with each of the addressable memory locations to select a single bit line associated with each memory location corresponding to the port input with the highest priority when more than one port input at the same addressable memory location carries an address select signal. Read address comparators and a data transfer unit operate to ensure that the data from the memory cells is also output to sense amplifiers corresponding to the non-selected lower priority port inputs.

Abstract: A computer-implemented method and apparatus in a computer system of processing data generated by a first application program in a second application program during runtime. During runtime, the first application program generates a record including a plurality of fields, wherein at least one of the plurality of fields contains data generated by the first application program. Other of the plurality of fields containing descriptive information regarding the data. The record also includes a reference (e.g. a pointer, relative or absolute) to a tag record. The tag record describes the plurality of fields contained in the record. The tag record further recursively references a plurality of tag records each referencing an associated tag record identifying fields in a referred-to tag record. This continues, recursively, until ultimately, a root record is referenced including a self-referential tag identifying the fields in the root record.

Abstract: A frame buffer designed to allow frame buffer operations which do not involve new row addresses to be accomplished without the need for a RAS cycle. The elimination of RAS cycles for address loading and similar functions substantially accelerates the operation of the frame buffer both as to functions which do not involve memory array addresses and those which do involve memory array addresses.

Abstract: A power management system for conserving power in a computer system that runs the UNIX.RTM. operating system. The power management system comprises a power management pseudo-device driver, power management compatible device drivers for power manageable hardware devices, and additions to the Device Driver Interface and Driver Kernel Interface (DDI/DKI) layer. Each power management compatible device driver maintains last access times for its associated hardware device components. The power management pseudo-device driver periodically checks the last access time for all the power manageable hardware device components in the computer system. If the power management pseudo-device driver determines that a hardware device component is idle, the power management pseudo-device driver instructs the idle hardware device's associated device driver to reduce power to the idle hardware device component.

Abstract: A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met.

Abstract: An electrical assembly which secures a detached cable/connector assembly to a substrate of a printed circuit board. The assembly has a printed circuit board that is mounted to a first surface of the substrate. The printed circuit board is coupled to an electrical connector assembly by a flexible cable. The electrical connector assembly can be plugged into an auxiliary device such as a CD-ROM. The electrical connector assembly has a tab that is inserted into an aperture located in the second surface of the substrate, to secure the connector assembly when the connector is not attached to the auxiliary device.

Abstract: A data processing system which utilizes dynamic memory that requires periodic refreshment includes a processor coupled to a memory controller which is in turn coupled to the dynamic memory. The memory controller includes a memory operation command queue for sequentially receiving memory operation commands from the processor and a refresh module for initiating refresh operations. The refresh module includes circuitry for initiating either a mandatory refresh operation or an optional refresh operation. Mandatory refresh operations are initiated at the conclusion of periodic intervals, unless an optional refresh operation has been initiated within the particular interval. An optional refresh operation is initiated within a particular interval if the memory operation command queue is empty. Optional refresh operations thereby serve to substitute for mandatory refresh operations, minimizing the system time lost to refresh operations.

Abstract: A central processing unit (CPU) is provided and is coupled to a display for displaying graphic and other data in multiple overlapping windows. The CPU is further coupled to one or more input devices which permits a user to selectively position a cursor and input and manipulate data within each of the windows on the display. The windows include defined areas having window features such as text, icons and buttons corresponding to functions to be executed by the CPU. Multiple applications may be executed concurrently by the CPU such that each application is associated with one or more windows. Each display element ("pixel") comprising the display is represented by multiple bits in a computer frame buffer memory coupled to the CPU. An alpha value (.alpha.) is associated with the intensity of each pixel of the display such that multiple images may be blended in accordance with a predefined formula utilizing the alpha values.

Abstract: Low threshold voltage MOS devices having asymmetric halo implants are disclosed herein. An asymmetric halo implant provides a pocket region located under a device's source or drain near where the source (or drain) edge abuts the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. Only the source or drain, not both, have the primary pocket region. An asymmetric halo device behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket implant is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET.

Abstract: A computer system including a central processing unit (CPU) and a power management circuit (PMC). The CPU has an active mode where it is responsive to interrupt and direct memory access requests, and a standby mode where it is in a low power state and is not responsive to the interrupts and direct memory access requests. The PMC monitors the interrupts and direct memory access requests in the system when the CPU is in the standby mode, and causes the CPU to enter the active mode upon the detection of either an interrupt or a direct memory access request.

Abstract: A packet filter can be programmed by a remote controller to detect packets meeting a particular criterion and to report detection of these packets to the controller. The reports from the packet filter are collected and analyzed by the remote controller. A streams module that incorporates the packet filter is used within a Solaris operating system environment that has been enhanced to support an object framework. The streams module exports a programming interface to the packet filter defined in an interface definition language (IDL). The streams module can be pushed onto a network device in a similar fashion to other streams modules. The streams module responds to requests from one remote controller or to requests from more than one remote controller. These remote controller requests arrive as remote procedure call (RPC) requests on the IDL object references exported by the module.

Abstract: A substrate, an alignment plate, a heat sink, a back plate, a plurality of spacers, and a plurality of nuts are used to removably package one or more semiconductor package into a single module. The semiconductor dies are packaged with tape automated bonding (TAB) packages having land grid array (LGA) outer lead bumps. The substrate comprises a number of land patterns, a number of alignment cavities, and a number of join cavities. The alignment plate is fabricated with a number of alignment pins, a number of housing cavities, and a number of join cavities. The heat sink is fabricated with a number of stems and a number of join cavities. The back plate is fabricated with a number of extrusions having threaded ends. The spacers are fabricated with flanged openings at both ends, and each spacer is loaded with a number of spring washers. The nuts are fabricated with stepped heads.

Abstract: Logic circuitry and a corresponding method for computing an indexed set address utilized by a cache to mitigate the probability of a conflict miss occurring for a given memory access. Implemented at component or system level, the logic circuitry performs pseudo-random indexing of a set address obtained from a memory address during a memory access by a processor unit. This is accomplished by performing operations consistent with modulo operations on the memory address.

Abstract: A substrate, an alignment plate, a heat sink, a back plate, a plurality of spacers, and a plurality of nuts are used to removably package one or more semiconductor package into a single module. The semiconductor dies are packaged with tape automated bonding (TAB) packages having land grid array (LGA) outer lead bumps. The substrate comprises a number of land patterns, a number of alignment cavities, and a number of join cavities. The alignment plate is fabricated with a number of alignment pins, a number of housing cavities, and a number of join cavities. The heat sink is fabricated with a number of stems and a number of join cavities. The back plate is fabricated with a number of extrusions having threaded ends. The spacers are fabricated with ranged openings at both ends, and each spacer is loaded with a number of spring washers. The nuts are fabricated with stepped heads.

Abstract: The present invention provides a mass storage system suitable for incorporation in a video-on-demand server that is capable of detecting and correct errors without a substantial increase in processor capacity or memory buffer size, and without any increase in disk input/output (I/O) bandwidth. The mass storage system includes a server controller, a cluster of data disk drives and a parity drive associated with the cluster of data disk drives. The controller provides video data streams to a number of viewers. Data is stored as contiguous data strips in the cluster of data drives. Each data strip includes a plurality of contiguous data slices logically distributed across the cluster of data drives. A plurality of parity slices, each parity slice corresponding to each data strip, is stored in the parity drive. When the failure of one of the data drives is detected, the parity drive is read in place of the failed drive.

Abstract: A parallel signal bus for conveying a plurality of logic signals with reduced Miller effect capacitance includes adjacent, parallel signal lines with inverting buffer amplifiers whose respective positions are staggered both longitudinally along the signal lines and latitudinally with respect to their adjacent signal lines. With such a staggered configuration, the resulting Miller effect capacitance which would otherwise result from adjacent signal lines being driven at opposing polarities is reduced, on average, by approximately half.

Abstract: A self-clocking sense amplifier includes first and second input nodes and first and second output nodes. A first N-Channel transistor has its drain connected to the first output node and its gate connected to the second output node. A second N-Channel transistor has its drain connected to the second output node and its gate connected to the first output node. An N-Channel pulldown transistor has its source connected to a first supply voltage potential, a drain connected to the drain of the first and second N-Channel transistors, and a gate connected to a pulldown node. A first P-Channel transistor has a source connected to the first input node, a drain connected to the first output node, and a gate connected to the second output node. A second P-Channel transistor has a source connected to the second input node, a drain connected to the second output node, and a gate connected to the first output node.

Abstract: A multiport memory cell has a pair of switched reference ports; a pair of banks having at least one switched read/write port; a storage element for storing a small differential voltage between one of the switched reference ports and a corresponding one of the switched read/write ports during a write operation; and a pair of amplifying elements for precharging bit line capacitances and/or providing sufficient output current during simultaneous read operations. During a read operation, the storage element is switched-on and swings high or low depending on the small differential voltage stored during the previous write operation.