Abstract: The present invention, a synchronizer, utlizes a plurality of clocking signals generated by a specialized clocking circuit, in conjunction with synchronizer modules incorporating transparent latches, to synchronize signals passing from a first clock domain to a second clock domain. Two types of synchronizer modules are disclosed, a single synchronizer module and a multiple synchronizer module. Both types of synchronizer modules utilize a "basic synchronizer cell" comprised of two transparent latches in series. The single synchronizer module is comprised of two such basic synchronizer cells, and utilizes a plurality of clocking signals which are coupled to the transparent latches to accomplish synchronization. The multiple synchronizer module, also utilizes a plurality of clocking signals, and is comprised of a plurality of single synchronizer modules coupled in parallel and a synchronizer selector circuit.

Abstract: An improved high speed bus and protocol are disclosed that are capable of transferring data in multiple modes. The bus is particularly useful in computer systems that require data transfer between a variety of computer peripheral memory devices. In base transfer mode, the bus is capable of a maximum of 32-bit data transfers while in extended transfer mode, the bus is capable of a maximum of 64-bit data transfers. The bus comprises a plurality of lines including address lines, size lines, data lines and various control lines. In its extended transfer mode, the bus is capable of employing a number of address and control lines as data transfer lines. The bus is also capable of disabling a device when the device is accessed in a transfer mode that the device does not support.

Abstract: A method for transitioning an Intel processor from virtual 8086 (V86) mode to protected mode operation which detects when a virtual V86 processor attempts to transition to protected mode, stores all of the information concerning the virtual processor at the time of the attempt to transition to protected mode, remaps the memory allotted to the virtual processor to the memory space used in running a process in real mode, sets up a dummy stack to provide for operation during a transition to protected mode, moves a process for transitioning to real memory space, shifts all of the register values to values for real memory space, and finally reactivates the transition to protected mode.

Abstract: An integral heat pipe, heat exchanger, and clamping plate. A base plate functioning as an evaporator has disposed in it a multiplicity of intersecting parallel and perpendicular internal channels extending laterally substantially across the base plate. A sintered copper thermal wick is applied to all channels. Thin-walled condenser tubes forming a condenser region are joined to the base plate at intersections of width wise and cross wise channels contained in the base plate. A multiplicity of fins extend to all condenser tubes. For heat pipe arrangements operating in horizontal configurations, all wick-lined channels within the base plate remain open. For heat pipe arrangements intended to operate in oblique or vertical configurations, horizontally extending channels vertically displaced relative to other horizontal channels are isolated from the latter by a multiplicity of plugs.

Abstract: An adaptive shading method is utilized to generate shaded images in real time. The technique to shade the image is determined according to the curvature of the surface, the variation of the light vector across the surface, and the variation of the eye vector across the surface. The color or intensity is first computed at each of the vertices of the polygon. A series of tests are then performed to determine the order equation that is to be used to interpolate the color or intensity across the polygon between the vertices. Using this technique, polygons having a slight or no curvature and an infinite light source (thus being the simplest form of shading), will use an extremely fast, low order equation to interpolate across the polygon. Polygons, having a high degree of curvature and/or positional light source will utilize, as necessary, a higher order equation which requires additional computation time but produces desirable shading results.

Abstract: In the system of the present invention, the limitations imposed by the physical limitations of the DMA controller are overcome by storing the channel control blocks in external memory. The DMA controller is programmed to reference a particular address of external memory when a predetermined bit in the current channel control block is set. The DMA controller will then perform a memory read operation on the area of memory referred to by that address in order to store the retrieved channel control block at a location previously utilized by a earlier channel control block. This reading process will continue until the bit is reset, at which time the DMA operation is complete. Dynamic chaining is accommodated whereby the channel control blocks can be dynamically changed during the DMA access to provide a flexible I/O system. Furthermore, a method and apparatus for implementing dynamic chaining without incurring race conditions is described.

Abstract: The present invention takes advantage of the hierarchical nature of the design to perform a hierarchical comparison on as many blocks and sub-blocks which can be matched between the layout and the logic design. Because the internal connections were previously verified when the first occurrence of the block was compared, repetition of lengthy comparisons of multiple occurrences of the same blocks in the designs is avoided and subsequent comparisons are performed simply by comparing the input and output connections to the block.

Abstract: An I/O write back cache memory and a data coherency method is provided to a computer system having a cache and a main memory. The data coherency method includes partitioning the main memory into memory segments, dynamically assigning and reassigning the ownership of the memory segments either to the cache memory or the I/O write back cache memory. The ownership of the memory segments controls the accessibility and cacheability of the memory segments for read and write cycles performed by the CPU and I/O devices. During reassignment, various data management actions are taken to ensure data coherency. As a result, the I/O devices can perform read and write cycles addressed against the cache and main memory in a manner that increases system performance with minimal increase in hardware and complexity cost.

Abstract: A method for allowing direct graphics access to backup storage areas in frame buffer memory used for retained windows and controlled by a graphics accelerator which includes the steps of establishing a shared memory file in system memory for the backup storage area indicating that the retained windows area initially exists in excess frame buffer memory, the shared memory file having storage to indicate the use of the shared area by a process; generating a page fault whenever access to the graphics accelerator is attempted and the state of another process is stored on the graphics accelerator; and calling a device driver in response to the page fault to switch the context stored on the graphics accelerator to that of the process attempting the access.

Abstract: A graphical user interface method wherein a user can retain frequently used menus on the display screen in an intuitive manner. A computer system is coupled to a display for displaying graphic and other data and to a pointer control device which permits a user to selectively position a pointer on the display and signal selections with a switch. Graphical menu buttons are displayed on the screen which correspond to menus displaying further functions. When a menu button is selected by the user, a menu appears in a rectangular box containing an icon of a pushpin and a plurality of menu choices which can be selected. If the user places the pointer over the pushpin icon and then releases the pointer control device switch, the icon of the pushpin is then modified so it appears that the pushpin has "pinned" the menu to the screen. The temporary menu box is converted into a permanent window which remains on the display regardless of other display operations.

Abstract: A method and apparatus for arbitrating among multiple requested data transfers based on the availability of transfer resources. A request for the control of a resource is transmitted to an arbiter with information regarding the size of data transfer, internal buses and external buses required. The arbiter compares the information with the space remaining in the buffer, internal bus availability and external bus availability. If all the resources are available to complete the request, then the request is granted arbitration and the requested transfer is started. If any of the resources is not available, the arbiter takes the next request for evaluation. A mechanism is also provided for each request to require the arbiter to wait until all the resources are available to prevent the arbiter from taking on the next request.

Abstract: A rename tracking and propagation facility propagates renames, executed in multiple isolated file system name spaces (FSNS), to a remote FSNS on a per object basis without corruption of the remote FSNS names. In propagating an object's rename, the smallest set of additional object's renames which must be applied in the remote FSNS in order to apply the object's rename in the remote FSNS is determined. The set of renames is applied in the correct order, in the remote FSNS, accounting for those renames already propagated to the remote FSNS. A record of renames executed in a FSNS is utilized to determine which renames are to propagated. To accommodate parallel development (multiple users modifying part of the fill system all the time without explicit locking), name collisions in the remote FSNS are detected and resolved. These sets of renames are constructed such that they can be applied to the remote FSNS in any order.

Abstract: A computer graphics system comprising apparatus for drawing quadrilateral images on an output display when furnished the vertices of the quadrilateral, apparatus for providing width values for each end of a line to be displayed on an output display which width values are indirectly related to the depth of the ends of the line from the viewer, and apparatus for utilizing the width values to determine vertices of a line to be drawn by the apparatus for drawing a quadrilateral image.

Abstract: A circuit for determining the carry out from the addition of two numbers independent of the determination of the sum of the two numbers including apparatus for determining a first carry out from each bit position for a carry in of a first value, apparatus for determining a second carry out from each bit position for a carry in of a second value, a plurality of apparatus for utilizing the first and second carry out values from two or more adjacent bit positions to produce a first carry out from each plurality of bit positions for a carry in of a first value, and second carry out from each plurality of bit positions for a carry in of a second value, and apparatus for selecting between the first and second values based on the actual values of the carry ins.

Abstract: The invention is an object-oriented graphic interface for use in computer controlled display systems. A central processing unit (CPU) is provided and is coupled to a display for displaying graphic and other data. The CPU is further coupled to a cursor control device which permits a user to selectively position a cursor at a desired location on the display, and signal the CPU of selections in accordance with the teachings of the present invention. Buttons are generated by the CPU and displayed which correspond to either a single function to be executed by the CPU, or a button stack which has associated therewith a plurality of functions disposed on a menu. The menu includes a plurality of buttons and/or button stacks. The menu also includes a first icon, which presently is in the form of a push pin. The placement of the cursor over the push pin and releasing the first switch on the cursor control results in the CPU converting the menu into a window.

Abstract: A cache controller is coupled between a central processing unit (CPU) and a memory management unit (MMU). The MMU is coupled to main memory, and the cache controller is further coupled to a cache memory. A cache controller transfers a block of N programming instructions from the main memory into the cache memory. Once this transfer is complete, the CPU begins the sequential execution of the N instructions. Generally concurrently, the cache controller scans each of the N instructions to detect branch instructions. Branch instructions are those instructions which require additional data not found within the block of N instructions previously loaded into the cache. Upon detection a branch instruction, and prior to the execution of the branch instruction by the CPU, the cache controller fetches the branch instruction data from main memory, and stores it within the cache.

Abstract: In a digital image processing system, a CPU and a memory is provided to an image signal processing subsystem for computing the output vector of an inverse discrete cosine transform. The inverse discrete cosine transform is represented as a linear system and the output vector is computed using a forward mapping procedure where system matrix columns scaled by the non-zero quantized corresponding transform domain coefficient selected from the input vector are successively accumulated into the output vector. Dequantizations and scalings are performed as a combined single step by looking up the kernel values of the scaled reconstruction kernels from lookup tables corresponding to the selected transform domain coefficients' positions in the input vector. The lookup tables are highly optimized exploiting the symmetry characteristics of the reconstruction kernels, the inherent properties of quantization and the statistical attributes of the quantized transform domain coefficients.