Abstract: A panel is provided with a plurality of breakout elements attached to one another, and the panel, by a plurality of tab-like protrusions formed on a non-viewable surface of the panel. The breakout elements are removed by twisting the tabs for the particular element to be removed, leaving any scoring resultant from tab removal on a non-viewed surface of the panel.

Abstract: A computer system with a number of subsystems or modules on separate circuit boards employs electronic keying to ensure proper configuration of these boards. A power key arrangement associated with a plug-in connector enables a separate power supply for each set of boards. A power supply turn-on signal is routed through a uniquely-configured connector path for each board, so the power supply turn-on is inhibited for improper configurations. The uniquely-configured connector path may use either a series or a parallel implementation. The series implementation employs a set of diodes connected for conduction in either of two directions, with the mating connector having its conductor paths connected to match the diode configuration; in this manner, the power supply enable signal can only flow through the series path if the proper board is plugged into a properly-coded slot, in which case the power supply to activate this board is activated through the series path including the diodes.

Abstract: An electronic module configured to removably receive a power cord is provided with an interlock mechanism that prevents the power cord from being attached or removed while the module is in a power-on or current-drawing condition. The electronic module includes an on/off switch that, when in its on state, places the electronic module in a power-on condition. A guard mechanism is mounted to the electronic module, proximate the power switch, and is movable from a first position that captures and holds the power cord in connected condition with the electronic module, or prevents connection with the electronic module, to a second position permitting removal or connection of the power cord. Movement of the guard mechanism from the first position to the second position is permitted only if the power switch is in an off state.

Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.

Abstract: A queue has a plurality of serially connected transparent latches forming individual storage locations. The queue includes an entry storage latch for receiving data signals into the queue and an exit storage latch for communicating data signals out from the queue. The output terminal of each latch is connected to the input terminal of a succeeding latch so that data signals received by the entry storage latch may propagate uninterruptedly through one or more storage latches to a predetermined storage location.

Abstract: A method for processing text in a system including a host computer having a central memory unit for storing text data and a terminal unit having a local memory and a keyboard for receiving operator inputs. The host computer transfers a portion of text data to the terminal unit local memory, the terminal unit generates text editing inputs to alter the data, and the data in the local memory are altered accordingly. The terminal unit assembles audit messages which indicate a fundamental operation requested by the text editing inputs, e.g., insert text, delete text, replace text, etc., and contain the information necessary for the host computer to effect it. The audit meassages are subsequently sent to the host computer so that the host computer may alter the text in the central memory unit according to the fundamental operation indicated by the audit message.

Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. Each CPU has a local memory, separate from the memory modules, and this local memory is of the dynamic type so it must be periodically refreshed.

Abstract: A system for folding the address space of a reserved segment of a high speed memory into a designated part of the address space of a cache memory included in the high speed memory. Folding information for distinguishing between cache entries that have been folded from reserved segments and those that normally map into a designated segment of the high speed memory is stored. The folding information is utilized to determine whether a cache miss occurs when the designated segment of the cache memory is accessed.

Abstract: A system for preventing voltage drops when a load circuit is connected and preventing arcing when a load is disconnected from an energized bus includes a current limit device and low impedance shunt that bypasses the current limit device when activated. The system activates the low impedance shunt only after a load capacitance is charged when the load is connected and deactivates the low impedance shunt prior to disconnecting the load.

Abstract: A circuit for controlling data transfer handshake protocol so that certain protocol events may occur prior to or simultaneously with the completion of a proceeding protocol event, and the ultimate results of the pending protocol event may be determined at a later time. In one embodiment of the invention a CPU operates to transfer data (either receive or send) between itself and an I/O channel every five processor clock cycles. At the beginning of each set of five clock cycles the CPU places data on the data bus and generates a transfer request (CPU-XFR) signal whenever it receives a data accepted (DATA-ACC) signal indicating that a previous data transfer has occurred. The CPU-XFR signal is generated regardless of whether or not the previous data transfer is complete at the time. The data transfer normally is completed one clock cycle after the CPU-XFR signal is generated, and at that time a transfer complete signal is generated.

Abstract: A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.

Abstract: A branch recovery mechanism completes the processing of a concurrently issued family of instructions depending on the location of the branch instruction in the family and on whether the branch was correctly predicted. If the branch was not correctly predicted, the writes and stores of instructions in the family the precede the branch instruction are completed and those instructions are retired. However, the writes and stores of the instructions in the family following the branch instruction are inhibited.

Abstract: A one out of N checking circuit for determining whether exactly one of N signal lines is active at any given time. The circuit includes a hierarchal structure of nodes which pairs the N signal lines together in a series of steps. Each node includes a par of output signal lines. The first signal line carries a signal representing whether an active signal line was "seen." The second signal line carries a signal representing whether an error has occurred, i.e. multiple active lines were seen. After each step, the number of signal lines is reduced by one-half until only two signal lines remain. At that point the two signal lines are compared and a final error signal is transmitted.

Abstract: An integrated circuit chip carries a number of electronic circuits, at least one of which includes, in its output stage, a control device that responds to a reference signal to adjust the output current-handling capability of the electronic circuit, thereby regulating the signal propagation delay exhibited by the electronic circuit. The reference circuit is generated by a digital-to-analog circuit that is also formed on the chip. The digital-to-analog circuit is coupled to a number of contact elements disposed on an outer surface of the package containing the integrated circuit chip that can be selectively interconnected to a DC voltage to choose the value of the reference signal.

Abstract: The present invention is directed to a self-calibrating clock synchronization system that receives a periodic, digital clock signal as a reference and generates therefrom a system clock signal that dynamically tracks and is synchronized to the reference clock. The invention utilizes state machine controlled selection circuitry that comprises a plurality of predetermined delays tapped to produce a number of phase-related clock signals, and multiplexing circuitry, for selecting one of the plurality of clock signals as the system clock. A comparator compares the selected clock signal and the reference clock to determine which leads or lags the other. In response to the comparison, selection, from the plurality of clock signals, of a system clock that most clearly matches the reference signal is made.

Abstract: A multiple power supply sensor for protecting shared processor buses in a multiprocessor system. In the case that a power failure or power supply malfunction occurs in one of the processors of the system, at least one of the shared processor buses will be isolated from the malfunctioning processor. As a result, data on that bus is not corrupted by the manfunctioning processor. The isolation is accomplished by independent sensor circuits present in each processor for each bus.

Abstract: Encoding and decoding circuits are described for functioning as both a time and voltage based transmission system. Multiple binary inputs can be transmitted and received on a single I/O pin by encoder and decoder circuits using high speed emitter coupled-like logic.

Abstract: A fixed entry-point map to produce an entry point address of a first micro-instruction for a particular macro-instruction. That address is then incremented by a fixed number to produce the second, third, etc. micro-instructions for that macro-instruction. In a first embodiment, after a fixed number of these address skips, the addresses are incremented by 1 so that successive micro-instructions are in adjacent address locations. In a second embodiment, the number of skips is variable.

Abstract: In a data processing system, a multiplication operation is immediately followed by a redundant multiplication operation, using the same, albeit altered, operands, to check the initial result. The initial result is immediately available for use, but the check is not performed until some time later. The original operands are altered for the redundant multiplication operation by shifting one operand 1 bit, and swapping them before multiplication.