Abstract: The method and means of transmitting a user's transaction message to a destination node in a computer-secured network operates on the message, and a sequence number that is unique to the transaction message to form a message authentication code in combination with the user's personal identification number. The message authentication code is encrypted with a generated random number and a single session encryption key which also encrypts the user's personal identification number. An intermediate node may receive the encryptions to reproduce the personal identification number that is then used to encrypt the received message and sequence number to produce the random number and a message authentication code for comparison with a decrypted message authentication code.

Abstract: A fault-tolerant computer system employs multiple identical CPUs executing the same instruction stream, each with their own independent memory. The multiple CPUs are loosely synchronized, as by counting events such as operating cycles and stalling any CPU ahead of others. Data output references via separate busses are voted at separate ports of each of the CPUs by voting circuits which detect when all CPUs have made the same reference, and only then pass on identical references to external I/O busses. The ports may include FIFO buffers to allow output references from the asynchronous CPUs to be handled as the CPUs load the FIFOs at different times. Input data to the CPUs from the I/O busses is not voted, but is buffered to allow the CPUs to accept it at their own clock rate.

Abstract: A fault-tolerant computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly shutdown, saving state to disk. A restart procedure restores the state existing at the time of power failure if the AC power has been restored by the time the shutdown is completed. This powerfail/autorestart procedure may be implemented in a fault-tolerant multiprocessor configuration having multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units.

Abstract: An electronic assembly includes an electronic module mountable to a backplane having a ground plane for grounding and EMI shielding. The electronic module includes a conductive chassis having a floating chassis board. Interface connectors are mounted to the chassis board and to the backplane and mate with one another when the electronic module engages the backplane. A grounding clip is mounted to the chassis board and is used to engage an alignment pin extending from the backplane. The grounding clip includes a laterally extending resilient arm which grounds the clip to the chassis. The alignment pin is electrically connected to the backplane ground plane and the grounding clip is electrically connected to the chassis board ground plane so that both ground planes are grounded to the chassis through the grounding clip. The backplane includes a ground pad which circumscribes the interface connectors and is connected to the ground plane.

Abstract: A synchronous processor unit is divided into two sections, and each separately clocked by different clock signals. One section, containing an instruction execution unit and memory for storage of instructions and data, is clocked at a higher frequency, while the other section, containing those elements of a processor unit less frequently used, are clocked with a slower-frequencied clock. The elements of each section are intercoupled by separate and independent data buses, and selectively to one another by a buffer unit. The clock signals used by both sections are produced by a clock-generating unit which also monitors the instructions being executed by the instruction execution unit. When an instruction requiring communication between the two sections is detected, at least one predetermined transition of each of the fast and slow clocks are synchronized, and during this synchronization the separate buses of each section are coupled to one another by the buffer unit for information exchanges therebetween.

Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.

Abstract: A computer system with a number of subsystems or modules on separate circuit boards employs electronic keying to ensure proper configuration of these boards. A power key arrangement associated with a plug-in connector enables a separate power supply for each set of boards. A power supply turn-on signal is routed through a uniquely-configured connector path for each board, so the power supply turn-on is inhibited for improper configurations. The uniquely-configured connector path may use either a series or a parallel implementation. The series implementation employs a set of diodes connected for conduction in either of two directions, with the mating connector having its conductor paths connected to match the diode configuration; in this manner, the power supply enable signal can only flow through the series path if the proper board is plugged into a properly-coded slot, in which case the power supply to activate this board is activated through the series path including the diodes.

Abstract: A method and process for providing a memory dump of less than the entire contents of memory is provided. The memory locations to be dumped are selected on the basis of recency of use, so that there is a high probability that portions of memory needed for analysis or evaluation of the computer system will be included in the selective dump. Preferably, the select ion is made on the basis of information or hardware which is already provided in the computer system. In one preferred embodiment, memory to be dumped is selected on the basis of memory locations encoded for by a translation lookaside buffer.

Abstract: A packaging system for components of a computing system includes an external, modularized, ecto-skeletal support frame for supporting a plurality of uniformly, horizontally dimensioned cabinets in stacked arrangement. The support frame is formed from a plurality of support shelves that form the support platforms for the cabinets. Separating and support shelves are support sleeves, that can be of variable lengths in order to accommodate the varying vertical dimensions of the cabinets held by the support frame.

Abstract: Disclosed is a circuit configuration that permits the monitoring of the operation of an input/output circuit of a digital unit under test by pseudo-random scan test techniques. A resistive element couples test signals to an input/output terminal of the device under test to which the input/output circuit is connected. The connection between the resistive element and the terminal is monitored during pseudo-random scan testing, permitting testing of the input/output circuitry.

Abstract: A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit ingress to and egress from function logic of the cell by neighboring cells. Each multiplexer is configured to receive and select between input and output busses from and to a neighbor cell adjacent the associated boundary. The output of each multiplexer connects to the output bus of the boundary adjacent to that with which the multiplexer is associated. When such cell architecture is used in wafer scale integration, oriented so that opposing sides of each cell are rotated 180 degrees relative to any cell at any boundary, the multiplexers can be configured to form a linear array of cells that ensures a fixed, known, delay from function logic to function logic of the cells.

Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. I/O devices are accessed through a pair of identical (redundant) I/O processors, but only one is designated to actively control a given device; in case of failure of one I/O processor, however, an I/O device can be accessed by the other one without system shutdown, i.e., by merely redesignating the addresses of the registers of the I/O device under instruction control.

Abstract: A tool (10) inserts and removes printed circuit boards (55) from a card cage (50) holding a plurality of such boards. The tool (10) has a guide (20), mounted on the card cage, a slider (30) slidably mounted to the guide, and lever arm (40), pivotally mounted to the slider. One tool can thus service all the printed circuit boards (55) in a card cage (50).

Abstract: A memory system is implemented by an array of large scale integrated dynamic random access memory elements. The memory elements are of a type that permit data way word storage on a page basis, each page being defined on a row boundary. Discovering that excess power consumption by the memory can result from successive memory operations made back-to-back to different page locations, the present invention provides counter means to count each immediately successive different page memory operations so that, when that count matches a maximum count, memory operations are stalled for a period of time.

Abstract: A bus controller, operable to grant access to a bus structure for communication between a number of individual processor modules interconnected by the bus to form a multiprocessor system, is also operable to determine the number of processors connected to the bus. The bus controller, in round-robin fashion, sequentially grants each processor access to the bus by commanding the processor to send data. The processor responds either by sending data in synchronism with a data clock supplied by the bus controller or, if no data is to be sent, responds with a no acknowledgment (NAK) signal. Initially, and periodically, the bus controller checks to determine the number of processors by, beginning with the highest identifying numbered processor, sending to that processor a send command, and looking for a response either in the form of data being sent or a NAK signal.

Abstract: A method and apparatus for synchronizing a plurality of processors. Each processor runs off of its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state. Each processor has a counter which counts the number of processor events indicated since the last time the processors were synchronized. When an event requiring synchronization is detected by a sync logic circuit associated with the processor, the sync logic circuit generates the wait signal after the next processor event. A compare circuit associated with each processor then tests the other event counters in the system and determines whether its associated processor is behind the others. If so, the sync logic circuit removes the wait signal until the next processor event. The processor is finally stopped when its event counter matches the event counter for the fastest processor.

Abstract: A multiprocessing computer system with data storage array systems allowing for linear and orthogonal expansion of data storage capacity and bandwidth by means of a switching network coupled between the data storage array systems and the multiple processors. The switching network provides the ability for any CPU to be directly coupled to any data storage array. By using the switching network to couple multiple CPU's to multiple data storage array systems, the computer system can be configured to optimally match the I/O bandwidth of the data storage array systems to the I/O performance of the CPU's.

Abstract: A high density electronic module packaging system includes a cabinet for housing a plurality of modules. Disposed at the rear of the cabinet and forming a rear wall thereof is a cooling system housing that is used for cooling the modules contained in the cabinet. Disposed within the cabinet are a plurality, e.g., four, cooling modules; a power distribution unit having a plurality, e.g., twelve, power converters; and a plurality, e.g., twenty-eight electronic modules. The number of cooling modules, power converters and electronic modules may be added or subtracted as needed or desired. The cooling modules flow cooling fluid to and/or from the power distribution unit and/or to the plurality of electronic modules. The power distribution unit supplies power to the plurality of electronic modules. The electronic modules may house one or more submodules such as storage devices (e.g., disk drives) or printed circuit boards.

Abstract: A high density electronic module packaging system includes a cabinet for housing a plurality of modules. Disposed at the rear of the cabinet and forming a rear wall thereof is a cooling system housing that is used for cooling the modules contained in the cabinet. Disposed within the cabinet are a plurality, e.g., four, cooling modules; a power distribution unit having a plurality, e.g., twelve, power converters; and a plurality, e.g., twenty-eight electronic modules. The number of cooling modules, power converters and electronic modules may be added or subtracted as needed or desired. The cooling modules flow cooling fluid to and/or from the power distribution unit and/or to the plurality of electronic modules. The power distribution unit supplies power to the plurality of electronic modules. The electronic modules may house one or more submodules such as storage devices (e.g., disk drives) or printed circuit boards.