Abstract: A method and apparatus for allowing a user to select and encrypt a Personal Identification Number (PIN) from a remote location without requiring clear transfer of the user-selected PIN and the account number during a single communication is disclosed. The preferred embodiment includes a host computer connected by a modem to a telephone line, along with appropriate communication software, and a security module connected to the host via a secure communication path. The security module generates an encrypted PIN using the user-selected PIN and a sequence number generated by the host. The security module can also processes the encrypted PIN and user account number to generate a Pin Verification Number (PVN) or other user authorization code. The PVN is subsequently used by a transaction system to verify the identity of the authorized user.

Abstract: Twisted wire pairs are used to interconnect units of a data processing system with connectors that incorporate electromagnetic interference suppression devices in the form of common mode ferrite choke.

Abstract: An apparatus and method for improving the input/output performance of a redundant storage array system. The present invention provides a "special parity" cache within the controller for a redundant storage array system, and means for determining and caching a quantity known as the "remaining redundancy row parity" (RRR-parity) block. The RRR-parity block is equal to the old parity block of a redundancy row XOR'd with an old data block being read from the same redundancy row. By caching RRR-parity blocks, Write-intensive storage unit operations can be reduced by up to three input/output accesses.

Abstract: An apparatus and method for monitoring the environment of remote components attached to a host processor by means of a standard interface bus having a limited number of address ports. The invention includes a host adapter incorporating a standard bus repeater component and an environment monitoring component. The environment monitoring component has a standard bus interface and is selectably coupled to the standard interface bus, and hence to a host processor. The host interface transceiver is coupled by means of a standard bus to the host processor, and is also selectably coupled to a drive interface transceiver by means of the standard bus. The drive interface transceiver is coupled by the standard bus to one or more storage devices. The host adapter is selectably switchable between two modes, such that either the drive interface transceiver is coupled through the host interface transceiver to the host processor, or the environment monitoring component is coupled to the host processor.

Abstract: A computer memory system is provided. Received memory requests can be for addresses which are virtual or physical. The type of address is determined, and a virtual/physical bit is set and stored. At least row address bits are compared to one or more registers which contain either a virtual or a physical row address, corresponding to a row addressed by a row address latch. When there is a hit with respect to one of these registers, column address bits are used to select the requested memory element, without the necessity for a virtual-to-physical translation. When there is a miss on all registers, a physical address is obtained, either from the requested address when this is physical, or from a virtual-to-physical translation. The physical address is used to load a new row address into a row address latch. Some column address bits are changed only when there has been a miss.

Abstract: A fault-tolerant computer system employs a pseudo-filesystem to dynamically manage the hardware components. A directory which appears as a standard, hierarchical directory in this filesystem contains a file for each component; each file maps to either a hardware component or a software module. The pseudo-filesystem hierarchy is determined during system initialization and is automatically updated whenever the software or hardware configuration changes. The pseudo-filesystem, called /config filesystem herein, is implemented as a Unix filesystem in the Unix filesystem switch. This pseudo-filesystem method may be implemented in a fault-tolerant, redundant computer system configuration having multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units.

Abstract: A fault tolerant power supply system for providing reliable power to a redundant array of data storage units. The system includes one power supply module for each channel of the array of data storage units. A power supply failure will not impact the ability of the data storage system to recover data due to the ability of the data storage system to reconstruct data in an unavailable channel from the data storage units of each other channel. The use of independent power supplies provides a power supply system which has a power capability equal to the sum of the power requirements of the data storage units, and voltage outputs just sufficient to meet the voltage requirements of the data storage units.

Abstract: The method and means of transmitting a user's transaction message to a destination node in a computer-secured network operates on the message, and a sequence number that is unique to the transaction message to form a message authentication code in combination with the user's personal identification number. The message authentication code is encrypted with a generated random number and a single session encryption key which also encrypts the user's personal identification number. An intermediate node may receive the encryptions to reproduce the personal identification number that is then used to encrypt the received message and sequence number to produce the random number and a message authentication code for comparison with a decrypted message authentication code.

Abstract: A fault-tolerant computer system employs multiple identical CPUs executing the same instruction stream, each with their own independent memory. The multiple CPUs are loosely synchronized, as by counting events such as operating cycles and stalling any CPU ahead of others. Data output references via separate busses are voted at separate ports of each of the CPUs by voting circuits which detect when all CPUs have made the same reference, and only then pass on identical references to external I/O busses. The ports may include FIFO buffers to allow output references from the asynchronous CPUs to be handled as the CPUs load the FIFOs at different times. Input data to the CPUs from the I/O busses is not voted, but is buffered to allow the CPUs to accept it at their own clock rate.

Abstract: A fault-tolerant computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly shutdown, saving state to disk. A restart procedure restores the state existing at the time of power failure if the AC power has been restored by the time the shutdown is completed. This powerfail/autorestart procedure may be implemented in a fault-tolerant multiprocessor configuration having multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units.

Abstract: An electronic assembly includes an electronic module mountable to a backplane having a ground plane for grounding and EMI shielding. The electronic module includes a conductive chassis having a floating chassis board. Interface connectors are mounted to the chassis board and to the backplane and mate with one another when the electronic module engages the backplane. A grounding clip is mounted to the chassis board and is used to engage an alignment pin extending from the backplane. The grounding clip includes a laterally extending resilient arm which grounds the clip to the chassis. The alignment pin is electrically connected to the backplane ground plane and the grounding clip is electrically connected to the chassis board ground plane so that both ground planes are grounded to the chassis through the grounding clip. The backplane includes a ground pad which circumscribes the interface connectors and is connected to the ground plane.

Abstract: A synchronous processor unit is divided into two sections, and each separately clocked by different clock signals. One section, containing an instruction execution unit and memory for storage of instructions and data, is clocked at a higher frequency, while the other section, containing those elements of a processor unit less frequently used, are clocked with a slower-frequencied clock. The elements of each section are intercoupled by separate and independent data buses, and selectively to one another by a buffer unit. The clock signals used by both sections are produced by a clock-generating unit which also monitors the instructions being executed by the instruction execution unit. When an instruction requiring communication between the two sections is detected, at least one predetermined transition of each of the fast and slow clocks are synchronized, and during this synchronization the separate buses of each section are coupled to one another by the buffer unit for information exchanges therebetween.

Abstract: A system and a method for implementing remote procedure calls in a distributed computer system provide a base object class from which all distributed objects can be derived. A program extracting all classes derived from the base class provides an inheritance tree to allow down casting from a root class to a base class and to allow passing high level data structure between participants of a remote procedure call. An Unix script provides stub routines for implementing a client-server model communicating processes.

Abstract: A computer system in a fault-tolerant configuration employs multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units. The faulty unit can be replaced and reintegrated into the system without shutdown. The multiple CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules.

Abstract: Disclosed is a circuit configuration that permits the monitoring of the operation of an input/output circuit of a digital unit under test by pseudo-random scan test techniques. A resistive element couples test signals to an input/output terminal of the device under test to which the input/output circuit is connected. The connection between the resistive element and the terminal is monitored during pseudo-random scan testing, permitting testing of the input/output circuitry.

Abstract: A packaging system for components of a computing system includes an external, modularized, ecto-skeletal support frame for supporting a plurality of uniformly, horizontally dimensioned cabinets in stacked arrangement. The support frame is formed from a plurality of support shelves that form the support platforms for the cabinets. Separating and support shelves are support sleeves, that can be of variable lengths in order to accommodate the varying vertical dimensions of the cabinets held by the support frame.

Abstract: A computer system with a number of subsystems or modules on separate circuit boards employs electronic keying to ensure proper configuration of these boards. A power key arrangement associated with a plug-in connector enables a separate power supply for each set of boards. A power supply turn-on signal is routed through a uniquely-configured connector path for each board, so the power supply turn-on is inhibited for improper configurations. The uniquely-configured connector path may use either a series or a parallel implementation. The series implementation employs a set of diodes connected for conduction in either of two directions, with the mating connector having its conductor paths connected to match the diode configuration; in this manner, the power supply enable signal can only flow through the series path if the proper board is plugged into a properly-coded slot, in which case the power supply to activate this board is activated through the series path including the diodes.

Abstract: A method and process for providing a memory dump of less than the entire contents of memory is provided. The memory locations to be dumped are selected on the basis of recency of use, so that there is a high probability that portions of memory needed for analysis or evaluation of the computer system will be included in the selective dump. Preferably, the select ion is made on the basis of information or hardware which is already provided in the computer system. In one preferred embodiment, memory to be dumped is selected on the basis of memory locations encoded for by a translation lookaside buffer.

Abstract: A high density electronic module packaging system includes a cabinet for housing a plurality of modules. Disposed at the rear of the cabinet and forming a rear wall thereof is a cooling system housing that is used for cooling the modules contained in the cabinet Disposed within the cabinet are a plurality, e.g., four, cooling modules; a power distribution unit having a plurality, e.g., twelve, power converters; and a plurality, e.g., twenty-eight electronic modules. The number of cooling modules, power converters and electronic modules may be added or subtracted as needed or desired. The cooling modules flow cooling fluid to and/or from the power distribution unit and/or to the plurality of electronic modules. The power distribution unit supplies power to the plurality of electronic modules. The electronic modules may house one or more submodules such as storage devices (e.g., disk drives) or printed circuit boards.

Abstract: A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit ingress to and egress from function logic of the cell by neighboring cells. Each multiplexer is configured to receive and select between input and output busses from and to a neighbor cell adjacent the associated boundary. The output of each multiplexer connects to the output bus of the boundary adjacent to that with which the multiplexer is associated. When such cell architecture is used in wafer scale integration, oriented so that opposing sides of each cell are rotated 180 degrees relative to any cell at any boundary, the multiplexers can be configured to form a linear array of cells that ensures a fixed, known, delay from function logic to function logic of the cells.