Patents Assigned to Technologies AG
  • Method of forming a semiconductor device and semiconductor device thereof
    Patent number: 7824973
    Abstract: According to one embodiment of the present invention, a method of forming a semiconductor device is provided, the method including: forming a substrate; forming a first gate on the substrate; forming a mask layer on the substrate, the mask layer including a first window covering an area within which the first gate is formed so that the first gate divides the substrate exposed by the first window into a first region and a second region; and doping the exposed substrate using rays inclined with respect to the substrate top surface, where the position of the first gate with respect to a border of the first window is chosen such that the inclined doping rays impinge more on the first region than on the second region.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventors: Karl Hofmann, Stefan Decker
  • Device to detect or generate optical signals
    Patent number: 7826062
    Abstract: The present invention relates to a device for detecting or generating and modulating optical signals, and having an angular dispersive element arranged to change angles of the optical signals or carrier and/or reference rays brought to interference.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: November 2, 2010
    Assignee: Campus Technologies AG
    Inventor: Thilo Weitzel
  • Multicast/broadcast extension to a point-to-point unicast-only packet switch system
    Patent number: 7826450
    Abstract: A method and system for routing a multicast packet through a unicast packet switch network of devices. A virtual destination group, which includes destination devices of the multicast packet, is defined, and then the virtual destination group is mapped to an unused unicast destination encoding in routing tables of the devices. The multicast packet is then routed from a source device to the destination devices using the routing tables.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventors: Jim Lin, Vijayasimha Kadamby
  • Method and apparatus for operating maskable memory cells
    Patent number: 7826299
    Abstract: A plurality of masked memory cells organized in at least two groups, each group using an individual mask signal, is operated by providing a logically valid mask signal only for a selected group comprising the memory cell to be accessed while a logically invalid mask signal are used for all groups other than the selected group.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kuenemund, Artur Wroblewski
  • Compensation for amplifiers driving a capacitive load
    Patent number: 7825732
    Abstract: This disclosure relates to load compensating multi-stage amplifier structures at an output of one of the amplifier stages.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventor: Dieter Draxelmayr
  • Method for filling a contact hole and integrated circuit arrangement with contact hole
    Patent number: 7825510
    Abstract: A method in which a base layer is deposited in a contact hole region under a protective gas, where base layer contains a nitride as main constituent. After the deposition of the base layer, a covering layer is deposited under gaseous nitrogen. An adhesion promoting layer results which is simple to produce and has good electrical properties.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventors: Jürgen Förster, Klemens Prügl, Berthold Schuderer
  • POLYURETHANE POLYMER FOR REVERSIBLE ADHESIVE BONDS
    Publication number: 20100273008
    Abstract: A polyurethane polymer which has sterically hindered urea groups which lead to the effect that the polyurethane has thermal lability at these sites. The invention further relates to a composition for preparing such a polyurethane polymer, said composition being suitable for the production of reversible adhesive bonds, seals and coatings. An inventive polyurethane polymer, or the corresponding composition for production thereof, finds use especially in automobile construction, where the possibility of detaching adhesive-bonded components and window panes is of significance for dismantling for repair purposes or else for utilization and recycling of used and accident-damaged automobiles.
    Type: Application
    Filed: November 21, 2008
    Publication date: October 28, 2010
    Applicant: SIKA Technology AG
    Inventor: Urs Burckhardt
  • INTERPOLE COUPLING SYSTEM
    Publication number: 20100270136
    Abstract: A circuit breaker includes a plurality of pole assemblies, each having a movable contact and a stationary contact. A bellcrank assembly is associated with each pole assembly. Each bellcrank assembly includes a bellcrank lever including a cylindrical body and at least one radially extending arm. The radially extending arm is mechanically interrelated with the movable contact so that rotation of the bellcrank lever selectively causes the movable contact to engage or disengage the stationary contact. At least one of the bellcrank lever radially extending arms is relatively more flexible than the other bellcrank lever radially extending arms.
    Type: Application
    Filed: April 13, 2010
    Publication date: October 28, 2010
    Applicant: AB Technology AG
    Inventor: Daniel J. Wolfe
  • Breaker with Improved Shipping Configuration
    Publication number: 20100270056
    Abstract: A pole assembly for a three phase breaker includes a center pole and a pair of outer poles positioned on opposed sides of the center pole. A pair of brackets are positioned at opposed ends of the pole, and include a center groove and a pair of outer grooves. The center pole is positioned in the center groove. The outer poles are secured in the outer groove in a shipping configuration and an installed configuration. When in the shipping configuration the bushings of all the poles are parallel. When in the installed configuration the bushings of the outer poles are angled away from the bushings of the center pole.
    Type: Application
    Filed: April 16, 2010
    Publication date: October 28, 2010
    Applicant: ABB Technology AG
    Inventors: Jason Stull, Vince Rogers, Christian Daehler
  • CURABLE COMPOSITIONS HAVING LESS VOLATILIZATION
    Publication number: 20100273924
    Abstract: The invention particularly relates to curable compositions comprising at least one polyisocyanate, at least one amine that is blocked by means of aldehyde or ketone, and at least one carboxylic acid hydrazide or sulfonic acid hydrazide which has a minimum melting point of 100° C., especially at least 150° C. Surprisingly, after being cured using moisture at room temperature and when being heated to increased temperatures, significantly fewer volatile components of such compositions volatilize than in the corresponding compositions that do not contain said hydrazide.
    Type: Application
    Filed: December 19, 2008
    Publication date: October 28, 2010
    Applicant: SIKA Technology AG
    Inventor: Urs Burckhardt
  • Analog to Digital Converter (ADC) with Comparator Function for Analog Signals
    Publication number: 20100271250
    Abstract: This disclosure relates to analog to digital converter (ADC) component with a comparator function for analog signals.
    Type: Application
    Filed: April 23, 2009
    Publication date: October 28, 2010
    Applicant: Infineon Technologies AG
    Inventors: Jens Barrenscheen, Karl Johann Schretter
  • METHOD FOR MANUFACTURING A REVERSE-CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR
    Publication number: 20100270585
    Abstract: A reverse-conducting insulated gate bipolar transistor includes a wafer of first conductivity type with a second layer of a second conductivity type and a third layer of the first conductivity type. A fifth electrically insulating layer partially covers these layers. An electrically conductive fourth layer is electrically insulated from the wafer by the fifth layer. The third through the fifth layers form a first opening above the second layer. A sixth layer of the second conductivity type and a seventh layer of the first conductivity type are arranged alternately in a plane on a second side of the wafer. A ninth layer is formed by implantation of ions through the first opening using the fourth and fifth layers as a first mask.
    Type: Application
    Filed: May 12, 2010
    Publication date: October 28, 2010
    Applicant: ABB Technology AG
    Inventors: Munaf RAHIMO, Jan Vobecky, Arnost Kopta
  • Dual mode radar methods and systems
    Patent number: 7821443
    Abstract: One embodiment relates to a dual mode radar transceiver. The dual mode transceiver includes a plurality of transmit channels. Each of the plurality of transmit channels is adapted to switch between a first mode and a second mode. The first mode includes a first combination of the plurality of transmit channels adapted to concurrently transmit outgoing signals. The second mode includes a plurality of different combinations of the plurality of transmit channels. Each of the plurality of different combinations has fewer transmit channels than the first combination. Other methods and systems are also disclosed.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: October 26, 2010
    Assignee: Infineon Technologies AG
    Inventors: Volker Winkler, Reinhard Feger
  • Fabrication and test methods and systems
    Patent number: 7821627
    Abstract: Methods and systems for fabricating and testing semiconductor devices are disclosed. In one embodiment, a method of forming a material includes providing a first workpiece, forming a material on the first workpiece using a first process condition, and measuring a defect state of the material using a test that utilizes a monochromatic light source. If the defect state is below a predetermined value, the material is formed on at least one second workpiece using the first process condition.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: October 26, 2010
    Assignee: Infineon Technologies AG
    Inventor: Hong-Jyh Li
  • Test structures and methods
    Patent number: 7820458
    Abstract: Test structures and methods for semiconductor devices, lithography systems, and lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes using a lithography system to expose a layer of photosensitive material of a workpiece to energy through a lithography mask, the lithography mask including a plurality of first test patterns having a first phase shift and at least one plurality of second test patterns having at least one second phase shift. The layer of photosensitive material of the workpiece is developed, and features formed on the layer of photosensitive material from the plurality of first test patterns and the at least one plurality of second test patterns are measured to determine a optimal focus level or optimal dose of the lithography system for exposing the layer of photosensitive material of the workpiece.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: October 26, 2010
    Assignee: Infineon Technologies AG
    Inventor: Sajan Marokkey
  • Switching apparatus and method for detecting an operating state
    Patent number: 7821319
    Abstract: A switching apparatus and method for detecting an operating state is disclosed. One embodiment has a MOS transistor, a replica of the MOS transistor and an evaluation arrangement and detects the start of switching of the MOS transistor by comparing the gate-source voltages of the transistors.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: October 26, 2010
    Assignee: Infineon Technologies AG
    Inventor: Steffen Thiele
  • Semiconductor device
    Patent number: 7821141
    Abstract: A semiconductor device including: a heat sink, a die on the heat sink, resin encapsulating the die, and a mounting aperture in the resin having at least a segment between the heat sink and a first end of the resin, wherein the thickness of the heat sink is no greater than 35% of the thickness of the device.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: October 26, 2010
    Assignee: Infineon Technologies AG
    Inventors: Wae Chet Yong, Teck Sim Lee, Erich Griebl, Mario Feldvoss, Juergen Schredl
  • Puffer circuit breaker with an overpressure valve
    Patent number: 7820933
    Abstract: A circuit breaker comprises a puffer volume (9) and at least one overpressure valve (16) for discharging gas from the puffer volume (9), if the pressure therein exceeds a given threshold. The overpressure valve (16) is formed by a piston (17) and a spring (19) as well as by a cavity (18) in the stationary support body (10) of the moveable contact assembly (2). The overpressure valve (16) is of compact and simple design, has low hysteresis and large cross-section.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: October 26, 2010
    Assignee: ABB Technology AG
    Inventors: Helmut Heiermeier, Kurt Kammerl, Timo Kehr, Stephan Grob
  • Transistor fabrication methods and structures thereof
    Patent number: 7820518
    Abstract: Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-inducing material over the gate, the gate dielectric, and the workpiece. Sidewall spacers are formed from the stress-inducing material on sidewalls of the gate and the gate dielectric.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: October 26, 2010
    Assignee: Infineon Technologies AG
    Inventors: Manfred Eller, Jiang Yan, Jin-Ping Han, Alois Gutmann
  • Module including a rough solder joint
    Patent number: 7821130
    Abstract: A module includes a metallized substrate including a metal layer, a base plate, and a joint joining the metal layer to the base plate. The joint includes solder contacting the base plate and an inter-metallic zone contacting the metal layer and the solder. The inter-metallic zone has spikes up to 100 ?m and a roughness (Rz) of at least 20 ?m.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: October 26, 2010
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Reinhold Bayerer