Abstract: A semiconductor component arrangement includes a power transistor and a temperature measurement circuit. The power transistor includes a gate electrode, a source zone, a drain zone and a body zone. The body zone is arranged in a first semiconductor zone of a first conduction type. The temperature measuring circuit comprises a temperature-dependent resistor and an evaluation circuit coupled to the temperature-dependent resistor. The resistor is formed by a portion of said first semiconductor zone.

Abstract: A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes routing a intracell wiring in at least one layer positioned above a substrate, with the conductors being spaced apart from one another so as to have gaps there between, and configuring and positioning a plurality of fill structures in the gaps. The method further includes arranging selected logic cells from the cell library to form a desired layout of the integrated circuit, routing interconnect wiring between the selected logic cells in the at least one layer, and removing fill structures at positions that conflict with the routing of the interconnect wiring.

Abstract: A semiconductor device and a method for producing it is disclosed. In one embodiment, an adhesion-promoting layer having nanoparticles is arranged between a circuit carrier and a plastic housing composition for the purpose of enhanced adhesion.

Abstract: An embodiment of a MIM capacitor includes a first insulating layer formed over a wafer and a first capacitor plate formed over the wafer within the first insulating layer. The MIM capacitor further includes a second insulating layer formed over the first insulating layer, a capacitor dielectric formed over the first capacitor plate within the second insulating layer and a second capacitor plate formed over the capacitor dielectric within the second insulating layer. A recess is formed in the second capacitor plate below an upper surface of the second insulating layer and a catalytic activation layer is formed in the recess.

Abstract: There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material.

Abstract: A system and method of calibrating optical line shortening measurements, and lithography mask for same. The lithography mask comprises a plurality of gratings, with a calibration marker disposed within each grating. The mask is used to pattern resist on a semiconductor wafer for purposes of measuring and calibrating line shortening. The pattern on the wafer is measured and compared to measurements made of the pattern on the mask. The difference gives the amount of line shortening due to flare, and may be used to calibrate line shortening measurements made using optical measurement tools.

Abstract: A fully operational digital protective relay or Intelligent Electronic Device (IED) are provided for protecting electrical equipment of a power distribution system. The relay includes an input module, a processing module and an output module. Signals received from current transformers connected to the input module are evaluated by the processing module, and in reaction thereto, trip signals can be output to an actuator of a circuit breaker via the output module. A base Human Machine Interface (HMI) enables a user to enter operating parameters such as a delay time or nominal current to the processing module. Optionally, a further HMI may be attached to the protective relay and connected, via a suitable interface for data exchange, to the processing module for the purpose of displaying protection-related information to a user. This further HMI is both optional and detachable. For example, the further HMI can be repeatedly attached to and detached from the protection device.

Abstract: The present invention concerns a system for the aftertreatment of parisons (7) produced in an injection molding mold, comprising at least two aftertreatment tools. To provide a system for the aftertreatment of parisons produced in an injection molding mold, by means of which a plurality of aftertreatment tools can be easily positioned, it is proposed in accordance with the invention that there is provided a positioning device for positioning the first aftertreatment tool in at least one positioning direction, and the at least two aftertreatment tools are connected together so that with the positioning device for positioning the first aftertreatment tool at least one further aftertreatment tool can be positioned by suitable positioning of the first aftertreatment tool.

Abstract: An electrical conductor carries a rated current in a high-current bushing of a transformer. The electrical conductor includes a conductor piece which extends along an axis and has a cylindrical envelope surface, a first electrical connection, and a second electrical connection. The first electrical connection has two contact surfaces which are aligned parallel to one another. Electrical losses of the electrical conductor are kept low, with a compact design. This is achieved, in part, because the second electrical connection is connected without a joint to the conductor piece, and the first electrical connection is hollow and, at right angles to the axis, has an oval profile with two longitudinal faces which form the two contact surfaces.

Abstract: A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer.

Abstract: A cavity member for a mold cavity structure for the production of hollow body moldings, wherein the cavity member has a substantially hollow-cylindrical element, wherein a cooling passage is provided at the outside of the hollow-cylindrical element. To provide a cavity member which is simple to manufacture and which permits more effective cooling of the cavity member it is proposed in accordance with the invention that there are provided one or more guide elements for forming the cooling passage, wherein the guide elements and the hollow-cylindrical element are in the form of separate parts.

Abstract: A method for manufacturing a reverse-conducting semiconductor device (RC-IGBT) with a seventh layer formed as a gate electrode and a first electrical contact on a emitter side and a second electrical contact on a collector side, which is opposite the emitter side, a wafer of a first conductivity type with a first side and a second side opposite the first side is provided. For the manufacturing of the RC-IGBT on the collector side, a first layer of the first conductivity type or of a second conductivity type is created on the second side. A mask with an opening is created on the first layer and those parts of the first layer, on which the opening of the mask is arranged, are removed. The remaining parts of the first layer form a third layer. Afterwards, for the manufacturing of a second layer of a different conductivity type than the third layer, ions are implanted into the wafer on the second side into those parts of the wafer, on which the at least one opening is arranged.

Abstract: A multifunction RF circuit on a single semiconductor chip. The multifunction RF circuit includes a power amplifier circuit, a mixer circuit forming an integral part of the power amplifier circuit and a low-pass filter circuit. The power amplifier circuit may include two amplifier circuits.

Abstract: A semiconductor component has a first and a second contact-making region, and a semiconductor volume arranged between the first and the second contact-making region. Within the semiconductor volume, it is possible to generate a current flow that runs from the first contact-making region to the second contact-making region, or vice versa. The semiconductor volume and/or the contact-making regions are configured in such a way that the local flow cross-section of a locally elevated current flow, which is caused by current splitting, is enlarged at least in partial regions of the semiconductor volume.

Abstract: A method for standardizing a reading taken on a fiber sample, including the steps of measuring a moisture content of the fiber sample, taking the reading on the fiber sample, and correcting the reading to a standardized reading that adjusts for a difference between the reading at the measured moisture content of the fiber sample and a standardized reading at about 7.5% moisture content.

Abstract: A semiconductor device and method is disclosed. One embodiment provides a substrate and a first semiconductor chip applied over the substrate. A first electrically conductive layer is applied over the substrate and the first semiconductor chip. A first electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the first electrically insulating layer.

Abstract: The invention relates to an apparatus for galvanically depositing an electrically conductive layer onto a carrier on which, at least in some regions, a starter layer suitable for electroplating is disposed. The apparatus has an electroplating bath in which an electrolyte for depositing conductive material is provided, at least two contact rollers which are disposed outside of the electroplating bath and which can be connected as cathode and/or anodes, and at least one deflection roller which is connected between the contact rollers, the position of the deflection roller being changeable between two contact rollers such that by changing the position of the deflection roller a distance to be covered by the carrier and which is formed between two contact points of two adjacent contact rollers corresponds to the extension of the starter layer to be coated.

Abstract: Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one radio frequency (RF) circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices.

Abstract: A method of manufacturing a semiconductor package with a bump using a carrier. One embodiment provides forming a bump on a carrier. A gap is formed in the carrier that undercuts the bump. A semiconductor chip is attached to the carrier. The chip is electrically connected to the bump. An encapsulant is deposited into the gap. The carrier is removed from the bump.