Abstract: A lithographic apparatus includes a machine table, a base, a placement table, a first baffle plate, a first driving device, and a transporting device. The machine table has a cavity formed by a side surface, a top surface, and a bottom surface. A conveying door is arranged on the side surface. A transferring device in the cavity can extend out from or retract back into the cavity through the conveying door. The placement table is configured to bear a mask carrier, and can at least extend out from or retract back to a bearing surface of the base. The first driving device is configured to drive the placement table to reciprocate between a first position and a second position.

Abstract: An external servo writer configured to write a plurality of embedded servo sectors on a magnetic tape to define a plurality of data tracks is disclosed. A first part of the plurality of embedded servo sectors is written while controlling an actuator to first move a head vertically along a width of the magnetic tape. A second part of the plurality of embedded servo sectors is written while controlling the actuator to second move the head vertically along the width of the magnetic tape.

Abstract: Methods and apparatus for use with non-volatile memory (NVM) arrays having single-level cell (SLC) layers and multi-level cell (MLC) layers, such as triple-level cell (TLC) layers, provide for a coupled SLC/MLC write operation where SLC write protection is combined into a MLC write flow. In an illustrative example, data is written concurrently to SLC and TLC. The SLC data provides a backup for the TLC data in the event the TLC data is defective. The TLC data is verified using, for example, write verification. If the data is successfully verified, the SLC block can be erased or otherwise overwritten with new data. If not, the SLC block can be used to recover the data for storage in a different TLC block. The coupled SLC/MLC write operation may be performed in conjunction with a quick pass write (QPW).

Abstract: A chemically modified cellulosic fibre or filament having a moisture content of at least 7% by weight obtained by a process comprising the steps of (i) obtaining cellulosic fibres or filament and chemically modifying the cellulose by substitution to increase its absorbency; (ii) washing the fibres after step (i) in a mixture comprising water and up to 99% by weight of water-miscible organic solvent; (iii) drying the fibres to a moisture content of at least 7% by weight.

Abstract: A magnetic head includes a medium facing surface, a main pole, a trailing shield, and a spin torque oscillator. A bottom surface of the trailing shield includes a first portion that includes an end located in the medium facing surface and is in contact with the spin torque oscillator at least in part. An element height that is a dimension of the spin torque oscillator in a direction perpendicular to the medium facing surface and a writer height that is a dimension of the first portion in the direction perpendicular to the medium facing surface are different from each other.

Abstract: The present disclosure generally relates to reducing time for interface transmitter training based upon an assumed identify of the training partner. It is unlikely for a drive PHY to link up with multiple PHYs per power cycle. Therefore, it is a fair assumption that when there is no power loss, the drive PHY is connected to the same host device. The drive can therefore change its behavior based on the assumed identity of the host from previously exchanged identify frames, if the previously used training algorithm was sufficient for interface transmitter training for the particular host. The drive will go directly to the correct training algorithm without the need to do a PHY reset using a training algorithm that is tailored to the host and thus reduce interface transmitter training time.

Abstract: A computer device associated with a vehicle pairs during an initial/setup pairing process with a UE device according to a wireless protocol. The devices exchange and store cryptographic information during pairing. Later, either device may detect/discover that the other is currently in its presence. Presence discovery may trigger the vehicle device to generate and broadcast an operational request message based on the cryptographic information, such as a public key of the UE, stored in the vehicle device. The UE receives the request, and transmits in response a vehicle operation permission message that it generates based on user input and cryptographic information, such as a public key of the vehicle device, stored by the UE during initial/setup pairing. The operational request message may be transmitted as an audio signal and received by a microphone of the UE. The vehicle device receives the permission message and generates an operation instruction based thereon.

Abstract: Mounting support assemblies for fire and overheat detection systems are described. The mounting support assemblies include a support tube connector having a first portion and a second portion, wherein a captive space is defined between the first portion and the second portion, a fastener arranged at least partially within the captive space and passing through the first portion of the support tube connector, and a biasing element arranged about the fastener and positioned between an end of the fastener and the first portion of the support tube connector, the biasing element biasing the fastener in a direction toward the second portion.

Abstract: A portable articulated arm coordinate measuring machine (AACMM) for measuring the coordinates of an object in space is provided. The AACMM includes a base and a manually positionable arm portion having an opposed first end and second end, the arm portion being rotationally coupled to the base, the arm portion including a plurality of connected arm segments, each arm segment including at least one position transducer for producing a position signal. A wire wound torsion spring is operably coupled between two of the connected arm segments. A first measurement probe is coupled to the first end, the first measurement probe having a first extension element. An electronic circuit is provided that receives the position signal from the at least one position transducer and provides data corresponding to a position of the first measurement probe. A probe end is disposed between the first measurement probe and the first end.

Abstract: A method for providing vehicle information includes: receiving first vehicle data encoded according to a first protocol and corresponding to an environment external to a vehicle; receiving high definition mapping data corresponding to objects in the environment external to the vehicle; generating position information for objects indicated in the high definition mapping data by correlating locations of objects indicated by the high definition mapping data with objects in the environment external to the vehicle detected by at least one sensor; generating second vehicle data by correlating the high definition mapping data, the position information, and the first vehicle data; and encoding the second vehicle data according to a second protocol.

Abstract: Embodiments of the innovation relate to, in a contact center apparatus, a method for identifying an incident associated with a service provided by a service provider. The method comprises: receiving real-time data from a data source, the real-time data identifying a reported incident associated with a service; applying the real-time data to an incident recognition model, the incident recognition model configured to identify a state of the service provided by the service provider; in response to applying the real-time data to an incident recognition model, identifying one of an absence of a service incident and a presence of a service incident associated with the service provider; and in response to identifying the presence of the service incident, outputting an incident notification to a contact center agent device.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate and a bit line structure located on the substrate, the bit line structure including a top dielectric layer and capacitive contact holes being provided on two opposite sides of the bit line structure; forming a first spacer covering a sidewall of the top dielectric layer between the bit line structure and the capacitive contact hole and a second spacer covering a sidewall of the first spacer, a top surface of the second spacer being higher than that of the first spacer; removing at least part of the top dielectric layer to form a first void; forming a first sealing film by a deposition process; and removing a part of the first sealing film which is higher than the top surface of the second spacer, the remaining first sealing film is a first sealing layer.

Abstract: A semiconductor structure manufacturing method includes: providing a substrate; forming a first insulating layer covering the substrate, and patterning the first insulating layer to form a plurality of vias and a plurality of isolation structures that are alternatingly distributed; forming conductive contact plugs in the vias respectively, where the conductive contact plugs cover bottoms of the vias and each includes a first region and a second region adjacent to each other, and the conductive contact plugs located in the first regions cover outer walls of the isolation structures and extend along the outer walls to surfaces of the isolation structures distal from the substrate; and forming a passivation layer covering side walls and surfaces of the conductive contact plugs.

Abstract: An interface circuit is configured to receive a data signal according to a data strobe signal. The method for evaluating performance of an interface circuit includes: a reference voltage of the interface circuit is scanned to obtain each reference voltage; a sampling point of the data signal by the data strobe signal to is scanned; a test result of the interface circuit under each reference voltage and each sampling point is obtained; and a data eye diagram is generated according to the test result. The performance of the interface circuit can be detected in combination with the scanning of the reference voltage.

Abstract: A method for manufacturing a memory device includes: a substrate is provided, the substrate including active regions; Bit Lines (BLs) are formed over the substrate, the BLs covering part of the active regions; a supporting layer is formed over the substrate covering the BLs and the substrate, first middle holes penetrating through the supporting layer and extending to the active regions are formed on the supporting layer, and gaps are formed between the first middle holes and the BLs; first protective layers are formed in the first middle holes, and etching holes which communicate with the substrate are formed in the first protective layers; the substrate and the active regions exposed in the etching holes are etched along the etching holes to form contact grooves; guide wires electrically connecting the active regions are formed in the first middle holes, the etching holes and the contact groove.

Abstract: A semiconductor structure includes: a substrate and a dielectric layer arranged on the substrate; a conductive plug, a first portion of the conductive plug being arranged in the substrate, and a second portion of the conductive plug being arranged in the dielectric layer; and a capacitor array, the capacitor array at least surrounding the second portion of the conductive plug.

Abstract: A semiconductor structure includes a substrate, bit line structures located on the substrate, capacitor contact holes located on each of two opposite sides of the bit line structure, and isolation side walls, each of the isolation side walls is located between a respective bit line structure and the capacitor contact holes on one side of the bit line structure. A gap isolation layer is provided between the isolation side walls located on two opposite sides of the bit line structure. The gap isolation layer is located on the bit line structure, and a first gap is provided inside the gap isolation layer. A second gap is provided between the isolation side wall and the gap isolation layer.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, an isolation trench being formed on the substrate; a silicon-rich isolation layer is formed in the isolation trench, the silicon-rich isolation layer covering an inner surface of the isolation trench; and an isolation oxide layer is formed in the isolation trench. The isolation oxide layer fills up the isolation trench.

Abstract: A data path interface circuit includes: a writing path module, connected to an internal port and an external port and configured to transmit stored data to the internal port from the external port; a reading path module, connected to the internal port and external port respectively and configured to transmit the stored data to the external port from the internal port; a first delay module, connected to the external port and internal port respectively, and configured to obtain the stored data from the external port or internal port, perform delay processing on the stored data, and transmit the delayed stored data to the writing path module and/or reading path module; and a delay control module, connected to the first delay module and configured to receive a signal instruction from external and control delay time for the first delay module to perform the delay processing according to the signal instruction.

Abstract: A mask includes a first boundary area and a plurality of exposure pattern areas, the first boundary area including a region surrounding the plurality of exposure pattern areas; in the first boundary area is disposed a plurality of first overlay mark units, each of which includes a plurality of overlay marks; the plurality of overlay marks are sequentially arranged along extension directions of adjacent transversal or longitudinal first boundary lines; a plurality of first overlay mark units are symmetric in pairs with a central line of the mask as a symmetric axis, and two symmetric first overlay mark units form an overlay mark set; arrangement directions of two overlay marks in the first overlay mark units in the same overlay mark set are parallel to and displaced with respect to each other.