Patents Assigned to TECHNOLOGIES INC.
  • Patent number: 11244920
    Abstract: Dies and/or wafers including conductive features at the bonding surfaces are stacked and direct hybrid bonded at a reduced temperature. The surface mobility and diffusion rates of the materials of the conductive features are manipulated by adjusting one or more of the metallographic texture or orientation at the surface of the conductive features and the concentration of impurities within the materials.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: February 8, 2022
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventor: Cyprian Emeka Uzoh
  • Publication number: 20220037479
    Abstract: A method for manufacturing an oxide layer includes: reacting a nitrogen-oxide-containing gas with hydrogen at a first temperature to form a first oxide layer, a volume concentration of the hydrogen in a first reaction gas being a first concentration; and reacting oxygen with hydrogen at a second temperature to form a second oxide layer on a surface of the first oxide layer, a volume concentration of the hydrogen in a second reaction gas being a second concentration; where the first temperature is less than the second temperature, and the first concentration is greater than the second concentration.
    Type: Application
    Filed: September 8, 2021
    Publication date: February 3, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Li ZHANG
  • Publication number: 20220037972
    Abstract: A stator assembly has coils in a distributed winding configuration. A poly-phase switched reluctance motor assembly may include a stator assembly with multiple coils in a distributed winding configuration. The stator assembly may have a central bore into which a rotor assembly having multiple poles is received and configured to rotate. A method of controlling a switched reluctance motor may include at least three phases wherein during each conduction period a first phase is energized with negative direction current, a second phase is energized with positive current and there is at least one non-energized phase. During each commutation period either the first phase or second phase switches off to a non-energized state and one of the non-energized phases switches on to an energized state with the same direction current as the first or second phase that was switched off. The switched reluctance motor may include a distributed winding configuration.
    Type: Application
    Filed: October 15, 2021
    Publication date: February 3, 2022
    Applicant: RESMED MOTOR TECHNOLOGIES INC.
    Inventors: Aleksandr S. Nagorny, Siavash Sadeghi, David James Fleming, Michael Bruce Moir
  • Publication number: 20220034939
    Abstract: A method for judging abnormality of a probe card includes: a unit failure rate of chips at the same test position in each measurement unit is obtained, and whether the unit failure rate of the chips at the same test position respectively meets the first abnormality condition is judged; when the unit failure rate of the chips at the same test position of each measurement unit meets a first abnormality condition, whether a test sequence for the measurement units meeting the first abnormality condition meets a second abnormality condition is judged; and when the test sequence for the measurement units meeting the first abnormality condition meets the second abnormality condition, it is determined that the probe card is abnormal.
    Type: Application
    Filed: August 23, 2021
    Publication date: February 3, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: CHENG-JER YANG
  • Publication number: 20220036995
    Abstract: In one embodiment, a computer-implemented system includes treatment apparatuses configured to be manipulated by patients while performing an exercise session, patient interfaces associated with the plurality of patients, and a server computing device configured to receive first characteristics pertaining to the patients, and initiate a virtual shared session on the patient interfaces associated with the patients. The virtual shared session includes at least a set of multimedia feeds, and each multimedia feed of the set of multimedia feeds is associated with one or more of the patients. During the virtual shared session, the server computing device may present a first layout including the set of multimedia feeds, the first characteristics, or some combination thereof.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 3, 2022
    Applicant: ROM TECHNOLOGIES, INC.
    Inventors: Steven Mason, Daniel Posnack, Peter Arn, Wendy Para, S. Adam Hacking, Micheal Mueller, Joseph Guaneri, Jonathan Greene
  • Publication number: 20220032347
    Abstract: A cleanup system for the semiconductor storage shelf is provided. A semiconductor storage shelf is provided with a plurality of stalls. The cleanup system for the semiconductor storage shelf includes a conveying device and a cleanup device. The cleanup device is configured to clean up each stall of the semiconductor storage shelf. The cleanup device is detachably connected to the conveying device. The conveying device is configured to convey the cleanup device to each stall of the semiconductor storage shelf.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 3, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yimo WANG
  • Publication number: 20220035238
    Abstract: A photolithography alignment method includes: performing alignment measurement of a surface condition of a wafer to obtain alignment information of the wafer; and sectioning the wafer into a plurality of areas to be processed according to the alignment information, and determining photolithography alignment parameters corresponding to each area to be processed.
    Type: Application
    Filed: October 19, 2021
    Publication date: February 3, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Lei ZHAO
  • Publication number: 20220037460
    Abstract: The present application relates to a fabrication method for a double-sided capacitor. The fabrication method for the double-sided capacitor includes the following steps: providing a substrate; forming a stack structure on the substrate; forming a capacitor hole in a direction perpendicular to the substrate to penetrate the stack structure, wherein the stack structure includes sacrificial layers and supporting layers alternately stacked; forming an auxiliary layer to cover the sidewall of the capacitor hole; forming a first electrode layer to cover the surface of the auxiliary layer; removing a part of the supporting layer on the top of the stack structure; removing the sacrificial layers and the auxiliary layer simultaneously along the opening; and forming a dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the surface of the dielectric layer, wherein the gap is at least filled with the dielectric layer.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 3, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yong LU
  • Publication number: 20220037481
    Abstract: Embodiments of the present application provide a semiconductor structure and its fabricating method, and a semiconductor memory. The method of fabricating a semiconductor structure comprises providing a substrate and performing ion implantation on the substrate to form an active area, forming a gate groove on surface of the substrate, measuring depth of the gate groove, and performing ion implantation compensation, if the depth of the gate groove meets a preset condition, on the substrate according to the depth of the gate groove, and forming an ion compensation region in the active area at one side of the gate groove.
    Type: Application
    Filed: October 13, 2021
    Publication date: February 3, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Bing ZOU, Cheng Yeh HSU
  • Publication number: 20220036988
    Abstract: A computer-implemented system includes a treatment apparatus configured to be manipulated by a patient while performing a treatment plan and a server computing device configured to execute an artificial intelligence engine to generate the treatment plan and a billing sequence associated with the treatment plan. The server computing device receives information pertaining to the patient, generates, based on the information, the treatment plan including instructions for the patient to follow, and receives a set of billing procedures associated with the instructions. The set of billing procedures includes rules pertaining to billing codes, timing, constraints, or some combination thereof. The server computing device generates, based on the set of billing procedures, the billing sequence for at least a portion of the instructions. The billing sequence is tailored according to a certain parameter. The server computing device transmits the treatment plan and the billing sequence to a computing device.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 3, 2022
    Applicant: ROM TECHNOLOGIES, INC.
    Inventors: Steven Mason, Daniel Posnack, Peter Arn, Wendy Para, S. Adam Hacking, Micheal Mueller, Joseph Guaneri, Jonathan Greene
  • Publication number: 20220037158
    Abstract: A method for forming a semiconductor structure includes: providing a substrate, a gate dielectric layer and an undoped polycrystalline silicon layer sequentially stacked; performing a thermal doping process, and doping first doping ions in the polycrystalline silicon layer; and performing an ion implantation process, and doping second doping ions in a preset region of the polycrystalline silicon layer. The preset region is spaced at a preset distance from a surface of the polycrystalline silicon layer away from the gate dielectric layer in a direction perpendicular to a surface of the substrate.
    Type: Application
    Filed: August 23, 2021
    Publication date: February 3, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: DAEJOONG WON
  • Publication number: 20220037330
    Abstract: A method for forming a memory device includes: after a hard mask layer is formed on a semiconductor substrate, a plurality of parallel mask patterns extending along a third direction are formed on the semiconductor substrate by adopting a self-alignment multi- pattern process, an opening is provided between the adjacent mask patterns, and the opening exposes surfaces of a plurality of drain regions and corresponding isolation layers in the third direction.
    Type: Application
    Filed: August 11, 2021
    Publication date: February 3, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Juanjuan HUANG, Lingxiang WANG
  • Publication number: 20220037161
    Abstract: A semiconductor etching method that comprises providing a material layer to be etched; sequentially forming on the material layer to be etched a first mask layer and a second mask layer that covers the first mask layer; patterning the second mask layer to form differently sized opening patterns that expose the first mask layer with differently sized regions; performing ion implantation on the exposed regions on the basis of the opening patterns; ion implantation concentration in each region is in direct proportion to the width of the region, and material etching removal rate of the ion-implanted region is in reverse proportion to the ion implantation concentration in the region; and basing on the opening patterns to etch the ion-implanted regions into the material layer to be etched to form grooves identical in size with the opening patterns, wherein depths of the grooves are approximate to or identical with one another.
    Type: Application
    Filed: October 14, 2021
    Publication date: February 3, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Lei YANG
  • Publication number: 20220037478
    Abstract: A buried wordline structure fabrication method includes: providing a first trench in a semiconductor substrate, wherein the first trench has a tip on its bottom; performing epitaxial growth within the first trench to reduce the depth of the tip on the bottom of the first trench; and forming a gate dielectric layer on an inner wall of the first trench and filling a gate conductive layer within the first trench to form the buried wordline structure.
    Type: Application
    Filed: August 21, 2021
    Publication date: February 3, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yong LU, Hongkun SHEN
  • Patent number: 11238595
    Abstract: An input image of an object is prepared for presentation by removing extraneous portions such as text, logos, advertising, watermarks, and so forth. The input image is processed to determined contours of features depicted in the input image. A bounding box corresponding to each contour may be determined. Based at least in part on the areas of these bounding boxes, an image mask is created. A candidate image is determined by applying the image mask to the input image to set pixels within portions of the input image to a predetermined value, such as white. Many candidate images may be generated using different parameters, such as different thresholds for relative sizes of the areas of the bounding boxes. These candidate images may be assessed, and a candidate image is selected for later use. Instead of manual editing of the input images, the candidate images are automatically generated.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: February 1, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Dibyendu Bhattacharya, Ravi Kumar, Sayantan Marik, Manisha Mehrotra, Mathieu Spegagne
  • Patent number: 11240539
    Abstract: Technologies are provided for reporting engaged impressions of directed content. Some embodiments include a computing device that can initiate a screensaver session within a content streaming service. The computing device also can cause presentation of a directed content asset on a display device functionally coupled to the computing device. The computing device can then update a queue to add a record of an impression of the directed content asset, where the queue is retained in a memory device of the computing device. The computing device can receive a signal indicative of user activity. The computing device can determine, using the queue, that the impression of the directed content asset occurred within a defined time interval relative to a time that the user activity occurred. The computing device can then send data identifying the directed content asset.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: February 1, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Salil Joshi, Ala Kallel, Yi Yao, Garrett Alan Dargan
  • Patent number: 11240621
    Abstract: A specification of a mesh of filters may be defined on a grid in a three-dimensional space presented in a user interface. A plurality of sound tracks may be determined, wherein each of the sound tracks is associated with a corresponding sound source that may be represented in the three-dimensional space along with a listener. Responsive to user configuration of a position of the listener and/or positions of the sound sources in the three-dimensional space, a plurality of filters may be selected based on the mesh of filters and the positions of the sound sources and the listener in the three-dimensional space. Each of the filters may be applied to a corresponding one of the plurality of sound tracks to generate a plurality of filtered sound tracks and the three-dimensional sound may be generated based on the plurality of filtered sound tracks.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: February 1, 2022
    Assignee: LI CREATIVE TECHNOLOGIES, INC.
    Inventors: Qi Li, Yin Ding, Jorel Olan, Jason Thai
  • Patent number: 11240456
    Abstract: An amplifier circuit for use in an image sensor includes a common source amplifier coupled to receive an input signal representative of an image charge from a pixel cell of the image sensor. An auto-zero switch is coupled between an input of the common source amplifier and an output of the common source amplifier. A feedback capacitor is coupled to the input of the common source amplifier. An offset switch is coupled to the feedback capacitor and is further coupled to a reset voltage and an output of the amplifier circuit. The auto-zero switch and the offset switch are configured to couple the feedback capacitor to the reset voltage during a reset of the amplifier circuit. The offset switch is configured to couple the feedback capacitor to the output of the amplifier circuit after the reset of the amplifier circuit.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 1, 2022
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Hiroaki Ebihara, Zheng Yang
  • Patent number: 11236631
    Abstract: Systems and methods are provided that use a tip clearance control apparatus comprising a mechanical iris, where the tip clearance control apparatus controls a distance between a tip of a blade and a ring of abradable material positioned in an adjustable opening of the mechanical iris.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 1, 2022
    Assignees: ROLLS-ROYCE NORTH AMERICAN TECHNOLOGIES INC., ROLLS-ROYCE CORPORATION
    Inventors: Richard Joseph Skertic, Joshua J. Gear, John Joseph Costello, Geoffrey L. Gatton
  • Patent number: 11240474
    Abstract: Systems and methods provide a notification of a connectivity problem of a video doorbell to a smartphone. A first communication link between the video doorbell and a backend server is determined unavailable, such as when a password used by the video doorbell to access a local area network (LAN) is not accepted by the LAN. A Bluetooth transceiver of the video doorbell is activated and a Bluetooth signal transmitted from the smartphone is detected. A second communication link between the video doorbell and the smartphone via the Bluetooth transceiver is established and a message is sent to the smartphone, via the Bluetooth transceiver, indicating that the password used by the video doorbell to access the LAN is not accepted by the LAN. The message causes an application running on the smartphone to display a notification on a display of the smartphone indicating the communication problem.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: February 1, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Elliott Lemberger, Joshua Hongpyo Yoon