Patents Assigned to TECHNOLOGIES INC.
  • Patent number: 11251814
    Abstract: A method and apparatus for obtaining data from a memory, estimating a probability of data values of the obtained data based on at least one of a source log-likelihood ratio and a channel log-likelihood ratio, wherein each bit in the obtained data has an associated log-likelihood ratio, determining at least one data pattern parameter for the data and performing a decoding process using the at least one data pattern parameters to determine a decoded data set.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: February 15, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Dudy David Avraham, Eran Sharon, Omer Fainzilber, Alexander Bazarsky, Stella Achtenberg
  • Patent number: 11252115
    Abstract: A conversation interface system provides remote access to manufacturing operation information using plain language message exchange. A cloud-based conversation interface service is exposed to an instant messaging application, and receives plain language queries from via the instant messaging application's interface requesting information relating to one or more industrial systems. The cloud-based system synchronizes the queries to one or more on-premise conversation interface agent devices residing at one or more plant facilities. The on-premise agent devices translate the queries and apply the translated queries to local sources of manufacturing operation data. The on-premise agent devices then generate and return response messages based on the retrieved information, and the cloud-based system directs the response messages the originators of the queries via the instant messaging interface.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: February 15, 2022
    Assignee: ROCKWELL AUTOMATION TECHNOLOGIES, INC.
    Inventors: Jonathan Wise, Petr Ptacek, David Wayne Comeau, Nancy Lynn Burnham, Jonathan D. Walter, Michael John Pantaleano, Eugene Liberman, Kenneth S. Plache
  • Patent number: 11247264
    Abstract: Provided are a multicore and a method of manufacturing a hollow product using the multicore enabling a hollow of a molded product to be molded more easily by casting and a quality problem to be addressed. The multicore includes a first core, being made of a water-insoluble material, having a hollow formed in the first core and, having an opening formed at both ends of the first core so that the hollow is exposed to the outside through the opening, a second core, being made of a water-soluble material and disposed inside the hollow, and a coating layer, being configured to surround the first core to prevent the first core and the second core from being exposed to an outside. Further, the first core includes a plurality of spaces to allow a fluid supplied to an interior of the first core to flow toward the second core.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: February 15, 2022
    Assignee: MH TECHNOLOGIES INC.
    Inventor: Jin-Ho Yoo
  • Patent number: 11252381
    Abstract: An image sensor includes a plurality of photodiodes, a plurality of color filters, and a plurality of microlenses. The plurality of photodiodes are arranged as a photodiode array, each of the plurality of photodiodes disposed within respective portions of a semiconductor material with a first lateral area. The plurality of color filters are arranged as a color filter array optically aligned with the photodiode array. Each of the plurality of color filters having a second lateral area greater than the first lateral area. The plurality of microlenses are arranged as a microlens array optically aligned with the color filter array and the photodiode array. Each of the plurality of microlenses have a third later area greater than the first lateral area and less than the second lateral area.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: February 15, 2022
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Chin Poh Pang, Guansong Liu, Xiaodong Yang, Boyang Zhang, Hongjun Li, Da Meng
  • Patent number: 11250520
    Abstract: Methods and systems for providing accounting services and corporate strategic planning services that comprise processing and aggregating financial transaction data and a plurality of input variables for maintaining a subscriber's general ledger, outputting audit ready financial reports, providing strategic planning inputs and by using at least one of semi-automated and machine learning algorithms are disclosed.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: February 15, 2022
    Assignee: FIN BOX TECHNOLOGIES, Inc.
    Inventors: Walter Drangmeister, R. Blake Ridgeway, Karen G. Stock, Charles J. Call
  • Patent number: 11250533
    Abstract: A publicly accessible urban beach entertainment complex is disclosed, with a man-made tropical, pristine-clear lagoon as the centerpiece of the complex, with surrounding entertainment, educational, sports, and commercial facilities, the complex having controlled public access and providing the look and feel of a tropical beach with clear waters and sandy beaches. In addition a method for efficiently utilizing facilities and land that are vacant, underutilized, have limited uses, or that are contiguous to or nearby recreational, educational, sports, or commercial venues is disclosed. The method providing a publicly accessible urban beach entertainment complex with a centerpiece man-made tropical-style pristine-clear lagoon. The method allows for generating revenue and increasing efficiency by pairing vacant sites, underutilized sites, limited use land, or sites that are contiguous to entertainment, educational, sports, and/or commercial venues with urban beach entertainment complexes.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 15, 2022
    Assignee: CRYSTAL LAGOONS TECHNOLOGIES, INC.
    Inventor: Fernando Benjamin Fischmann
  • Patent number: 11250913
    Abstract: Aspects of a storage device including a memory and a controller are provided which allow for efficient programming of cells on word lines using different scrambling seeds. The controller attempts to program cells of the memory by applying data scrambled using a first scrambling seed to the word line. If this attempt to program fails, the controller scrambles the data using a second, different scrambling seed and attempts to program the cells by applying the re-scrambled data to the word line. If this re-attempt also fails, the word line is listed. Then when the controller receives other data, the controller performs a final programming attempt with the other data scrambled using the second scrambling seed. If this further attempt fails, the controller identifies the block including the failed word line as a GBB. Thus, fewer GBBs may be incorrectly identified, reducing DPPM and improving memory yield of the storage device.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: February 15, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sudipta Dutta, Amiya Banerjee
  • Patent number: 11252273
    Abstract: A community safety system (CSS) including a notification management entity (NME) comprising servers, the NME communicatively coupled to multiple user devices and one or more administrator devices (collectively, registered user devices). The CSS includes a plurality of registered users, wherein registered users may share their own location, as well as sighting information about the location of a source of an emergency (e.g. a perpetrator) with the NME of the CSS. The NME may generate and provide display objects on a visualization interface of one or more users mobile devices displaying a map, the display objects indicative of user locations and/or emergency source location in the map displayed (e.g., in accordance with the map coordinate system).
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: February 15, 2022
    Assignee: TITAN HEALTH & SECURITY TECHNOLOGIES, INC.
    Inventors: Vic A. Merjanian, Ryan Khalili, Eduardo Juarez, Ed Merjanian, Serene Nasser, Daniel Wallengren
  • Patent number: 11249894
    Abstract: A storage device includes a flash memory array and a controller. The flash memory array includes a plurality of blocks. A minimal erase number of blocks have a minimal erase count in the plurality of blocks. When one of the minimal erase number of blocks is erased, the controller subtracts 1 from the minimal erase number.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: February 15, 2022
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Zhongyi Gao, Xiaoyu Yang
  • Patent number: 11249790
    Abstract: Generally described, one or more aspects of the present application relate to an instance resource oversubscription service for scheduling a burst period for a running virtual machine instance based on a time window specified by a user of the virtual machine instance. For example, the instance resource oversubscription service can predict future resource usage and identify the appropriate timing and physical host machine for letting the user burst (e.g., temporarily use the virtual machine instance in a manner than consumes a higher amount of computing resources such as CPU cycles, memory, network bandwidth, etc.). In doing so, the instance resource oversubscription service may consider, for example, the historical and current resource utilization levels of the virtual machine instances running on a set of available physical host machines and the burst period scheduling requests from other users of the instance resource oversubscription service.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: February 15, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Diwakar Gupta, Alexey Gadalin, Ethan John Faust
  • Patent number: 11250892
    Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current during program operations using pre-charge ramp rate control based on an inhibit bit line count acquired from data latches. When the inhibit bit line count is within a bit line count range, the controller pre-charges bit lines in memory at a first ramp rate to a first target voltage, and when the inhibit bit line count is outside the bit line count range, the controller pre-charges the bit lines at a second, faster ramp rate to a second, smaller target voltage. The inhibit bit line count may increase throughout a program operation, and the bit line count range may be configured for the middle of the program operation where current is typically high. Thus, a balance in power consumption and performance may be achieved during program operations using ramp rate control.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: February 15, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yu-Chung Lien, Juan Lee, Huai-Yuan Tseng
  • Patent number: 11252097
    Abstract: Techniques for oscillatory complementary network property calibration of a network connection can be implemented by measuring a first network property (e.g., latency or bandwidth output) as a function of bandwidth input and performing statistical analysis to determine a correlation. If a non-zero correlation coefficient is detected, a second network property complementary to the first network property can be measured to determine a first value of the second network property. Likewise, the second network property can be measured as a function of bandwidth input to determine a second correlation which, if positive, may indicate how to determine a second value of the first network property. The first value and the second value can be utilized to determine a third value of a third network property (e.g., network latency and network capacity utilized to determine bandwidth-delay product).
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 15, 2022
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: James Morgan Selvidge, Stephen Daniel Vilke, Paul Hinks, Rudy Willis
  • Publication number: 20220042509
    Abstract: A compressor (10) includes a compression mechanism (18) and a driveshaft (62) that drives the compression mechanism (18). The driveshaft (62) may include a first axially extending passage (94), a second axially extending passage (96), and a lubricant distribution passage (100). The first and second axially extending passages (94, 96) may be radially offset from each other and may intersect each other at an overlap region (98). The first and second axially extending passages (94, 96) are in fluid communication with each other at the overlap region (98). The lubricant distribution passage (100) may extend from the first axially extending passage (94) through an outer diametrical surface of the driveshaft (62). The lubricant distribution passage (100) may be disposed at a first axial distance (D1) from a first axial end (90) of the driveshaft (62). A first axial end of the overlap region (98) may be disposed at a second axial distance (D2) from the first axial end (90) of the drive shaft (62).
    Type: Application
    Filed: September 28, 2018
    Publication date: February 10, 2022
    Applicant: EMERSON CLIMATE TECHNOLOGIES, INC.
    Inventors: Jesus Angel NOHALES HERRAIZ, Xiaogeng SU, Sheng LIANG
  • Publication number: 20220042969
    Abstract: The present invention relates to methods for controlling chromatographic processes in real-time via mass measurement utilizing a variable pathlength spectrophotometer.
    Type: Application
    Filed: October 8, 2019
    Publication date: February 10, 2022
    Applicant: C TECHNOLOGIES, INC.
    Inventors: Craig Harrison, Ramsey Shanbaky
  • Publication number: 20220045186
    Abstract: A semiconductor structure includes: a substrate with conductive contact regions; a bit line structure and an isolation wall located on a sidewall of the bit line structure, the isolation wall includes at least one isolation layer including a first isolation part close to the bit line structure and a second isolation part deviating from the same, the second isolation part has doped ions, such that it has a greater hardness than the first isolation part, or has a smaller dielectric constant than the first isolation part; and a capacitor contact hole, which exposes the conductive contact region, and has a top width greater than a bottom width in a direction parallel to an orientation of the bit line structure.
    Type: Application
    Filed: September 30, 2021
    Publication date: February 10, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jingwen LU
  • Publication number: 20220045071
    Abstract: A semiconductor structure includes a substrate, an isolation structure formed in the substrate, and a word line including a first convex portion and a second convex portion. The first convex portion and the second convex portion are located in the isolation structure, and a depth of the first convex portion is greater than a depth of the second convex portion.
    Type: Application
    Filed: August 18, 2021
    Publication date: February 10, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yachuan HE, Hsin-Pin HUANG
  • Publication number: 20220045675
    Abstract: A driving circuit includes: a primary driving module configured to receive a first signal and generate a second signal based on the first signal, driving capability of the second signal being greater than that of the first signal; and an auxiliary driving module connected to an output terminal of the primary driving module and configured to receive the first signal and generate an auxiliary driving signal based on the first signal, the auxiliary driving signal being configured to shorten a rise time of the second signal.
    Type: Application
    Filed: July 14, 2021
    Publication date: February 10, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yinchuan GU
  • Publication number: 20220043051
    Abstract: A testing method includes: a wafer under test is detected based on a pre-set test region to obtain detection results of a plurality of chips in the wafer under test; a discrete point distribution diagram of the detection results of the plurality of chips are obtained, a discrete point in the discrete point distribution diagram being used for representing a position of an abnormal chip in the wafer under test; the discrete point distribution diagram is divided into a plurality of test regions based on graphic distribution characteristics in the pre-set test region, and a test result distribution diagram for representing graphic characteristics of the discrete point distribution diagram is obtained; a correlation between the test result distribution diagram and the graphic distribution characteristics in the pre-set test region is obtained; and a test result of the wafer under test is obtained based on the correlation.
    Type: Application
    Filed: August 25, 2021
    Publication date: February 10, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yu-Ting CHENG
  • Publication number: 20220044786
    Abstract: A method is disclosed for generating treatment plans for optimizing patient outcome and monetary value amount generated. The method includes receiving a set of treatment plans that, when applied to patients, cause outcomes to be achieved by the patients, receiving a set of monetary value amounts associated with the set of treatment plans, receiving a set of constraints, where the set of constraints comprises rules pertaining to billing codes associated with the set of treatment plans. The method includes generating, by the artificial intelligence engine, optimal treatment plans for a patient, where the generating is based on the set of treatment plans, the set of monetary value amounts, and the set of constraints. Each of the optimal treatment plans complies with the set of constraints and represents a patient outcome and an associated monetary value amount generated. The method includes transmitting the optimal treatment plans to a computing device.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 10, 2022
    Applicant: ROM TECHNOLOGIES, INC.
    Inventor: Steven Mason
  • Publication number: 20220045669
    Abstract: A comparator includes: a first stage circuit, configured to receive a voltage signal to be compared and a reference voltage signal Vref, and to generate and output a first amplifying signal and a second amplifying signal based on the voltage signal to be compared and the reference voltage signal Vref; a second stage circuit, connected with the first stage circuit, configured to generate and latch a first output signal and a second output signal based on the first amplifying signal and the second amplifying signal; wherein the first stage circuit and/or the second stage circuit include(s) a first pair of cross-coupled transistors.
    Type: Application
    Filed: August 21, 2021
    Publication date: February 10, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xiaofei CHEN