Abstract: A memory including various selectively configurable peripherals which provide on-chip low-level control features and a configuration RAM storing bits which both provide unclocked full logic-level outputs to control the selectively configurable peripherals and can also be accessed and read out. That is, each cell in the configuration RAM has two output modes: a digital continuous output, which is provided as a continuous control signal to various peripheral circuits and a selectable analog output which is used to read the information stored in the configuration RAM.

Abstract: In stacked CMOS, a single gate in first level polycrystalline silicon is used to address both an N-channel device in the substrate and an overlaid p-channel device. The p-channel device has self-aligned source and drain regions formed by diffusing a dopant from doped regions underlying them. The doped regions are formed by planarizing a doped insulating layer, and etching the doped layer back to the upper level of the gate prior to deposition of a second polysilicon layer.

Abstract: In a darlington transistor having an integrated resistor connected from base to emitter of the output transistor element, the effect of the diode between collector and emitter formed when the resistor consists of an extension to the base region is reduced by forming at least part of the resistor either as an extension to the emitter region or as a separate region of the same conductivity type and connected to it. The resistor formed by the emitter region material appears in series with the diode.

Abstract: A memory for generating data signals responsive to a select signal, a means for generating an increment signal responsive to particular ones of the data signals, a counter for selectively outputting the select signal corresponding to a stored count value, and a means for selectively incrementing the stored count value in the counter responsive to the increment signal. In a preferred embodiment, the data processing system includes means for selectively generating first and second enable signals responsive to particular ones of the data signals and includes, a first counter for selectively generating a select signal corresponding to a stored count value responsive to the first enable signal and a second counter for selectively generating the select signal corresponding to a stored count value responsive to the second enable signal.

Abstract: A digital processing system including a nonvolatile memory for the storage of instructions and data where the memory contains a plurality of field effect transistors which selectively conduct current according to the electrical state of their gates and the doping of their channel regions. Also included is a central processing unit for performing operations on data connected to an information transfer bus which is in turn connected to the nonvolatile memory. The information bus is additionally connected to an external interface circuit that provides interface to external peripherals. The memory is programmed by the doping of the channel regions instead of the fabrication or nonfabrication of the gates. Therefore, data that is stored in the memory is invisible to one examining the memory itself. This allows protection to software stored in the permanently programmed memory.

Abstract: A current switch whose turn-on and turn-off voltages are independent of temperature includes a transistor switch circuit having two input transistors to which a differential voltage is applied, two sensing transistors for sensing turn-on and turn-off voltages respectively, and an output transistor controlled by the sensing transistors. A differential voltage sensing circuit including a differential transistor pair is connected to receive the differential voltage at the inputs of the transistors and to deliver the differential voltage to the transistor switch circuit. A biasing current source is provided to supply biasing currents which vary as a function of temperature to the input and sensing transistors of the switch circuit, and a biasing current source is provided to supply a biasing current which varies as a function of temperature squared to the differential transistor pair.

Abstract: There is disclosed a method and apparatus for decoding coded information such as may be provided by a printed bar code. The coded information is segmented into a plurality of words, each having more bits than the number of bits appearing in the corresponding decoded word. The bits of each coded word are subdivided into at least two partial coded words. Each of these partial coded words is then decoded and the decoded versions for all the partial coded words combined so as to yield the decoded word. In the preferred embodiment the method of combination is summation of the decoded partial coded words.

Abstract: An over-the-shoulder automotive safety seat belt system having a latch providing a tensionless comfort setting for the belt during use and having remotely operable thermostat metal means to release the latch and permit automatic belt retraction after use is shown to have an improved electrically operable latch release mechanism providing reliable latching and providing fast and reliable latch release operation at low power levels.

Abstract: A stiffened composite metal panel is made by providing a layer of metal with spaced grooves of a depth less than the thickness of the metal layer for defining separable strips of the layer and, after arranging stripes of bond-preventing material between limited portions of the respective separable strips and a second metal layer, the metal layers are passed between pressure bonding rolls with reduction in the thickness of the layer materials to metallurgically bond a portion of each separable strip to the second metal layer to form a composite metal panel while leaving a portion of each separable strip free of such bonding at the location of the bond-preventing stripe. The separable strips are then broken apart along the grooves and folded away from the second metal layer to form precisely located stiffening ribs in the composite panel.

Abstract: Contact elements depending from a continuous carrier strip along with an interliner are helically wound on a reel in order to provide a sufficient supply of such elements for use with high speed assembly apparatus in which the contact elements are mounted in socket bodies in a continuous fashion. Upper and lower traverse winding stations each include a traversing mechanism mounting an interliner guide and an aligned carrier strip guide. The carrier strip guide is pivotably mounted and has an elliptical tube which extends to the core of the reel and is adapted to follow the diameter of the core as it builds up with layers of carrier strips and interliner and has a carrier strip receiving end which is configured such that a smooth transition surface is presented to the carrier strip in any position the guide assumes.

Abstract: A byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the externally received column address and the stored defective-column-address is found, the sense amplifier for the bit position which contains that defective column is disabled, and the output of the redundant column (selected by whichever word line is activated) is multiplexed into the I-O buss. Thus, before the row address signal has even been decoded, the defective column has been disabled and one of the redundant columns has effectively been substituted. This configuration means that it is not necessary to have one redundant column for every bit position, but each redundant column can substitute for a defective column in any bit position, and more than one defective column in a single bit position can each be replaced.

Abstract: Apparatus for testing high density VLSI memory elements of a semiconductor chip having bit line connections to at least selected ones of which includes a parallel signature analyzer built onto the chip adjacent the memory elements and connected to at least some of them by the bit line connections. The parallel signature analyzer is configurable to apply selected signals onto the bit lines in one mode to enable test signals to be written into selected memory cells to generate preselected memory states therewithin. The parallel signature analyzer is also configurable, in another mode to read the states of the memory cells and to develop a signature of the states read to indicate whether the selectively applied signals were properly written into and read from the high density memory. Means are also provided for delivering the signature to an output lead in the form of a quotient bit, if desired.

Abstract: Using the present invention, a gate for a MESFET may be fabricated having a minimum gate length while having a low resistance gate. In addition, the present invention provides a method for forming a gate and gate recess which are perfectly aligned which is the optimal structure for high frequency power MESFETs. A two layer masking layer is fabricated having a first layer which may be etched uniformly and a second layer of lithographic material which may be photolithographic material such as AZ resist. A gate opening is patterned in the photoresist material and a metal such as gold is deposited by evaporation from acute angles on opposite sides of the gate opening in the resist. The deposited metal serves as a mask which covers all but a very small portion of the opening in the photoresist. The silicon nitride layer is then etched to form a gate opening and gate recess.

Abstract: The disclosure relates to a method of growing thermal oxide on silicon wherein the oxide is grown at an increased rate, at reduced temperature or a combination thereof. This is accomplished by operating in an hermetic quartz tube capable of withstanding high pressure with steam or oxygen at super atmospheric pressure.

Abstract: Gates of individual devices on a slice are connected through a resistance to the device substrate, and through the same resistance to other device gates. This interconnection and high-resistance drain gives the gate protection from static charge buildup and subsequent catastrophic discharge which would result in a faulty device. This method protects each gate from the time of deposition to final device packaging.

Abstract: An electric component such as a rectifier is shown in which the electric leads are formed from composite wire material. The wire material has a copper core surrounded by and metallurgically bonded to a layer of ferrous material such as steel having optimal concentricity which layer is in turn surrounded by and metallurgically bonded to a layer of copper.

Abstract: An integrated on/off switch is provided that includes a latch that prevents the consumption of power by the switch during an "off" state. The switch circuits also includes the capability connected to the latch to activate a power supply during an "on" state and deactivate the power supply during the occurrence of an "off" state. Additionally the switch circuit includes the capability to reduce the direct current of the switch circuitry during "on" state. Lastly, the circuit includes the capability to alter the state of the latch upon the occurrence of a "off" signal or "on" signal. This switch can be monolithically integrated on a semiconductor substrate.

Abstract: Isolation trenches are formed around selected areas on an integrated circuit device, and highly doped areas are formed in the epitaxial silicon surrounding such trenches. The device is then oxidized at a low temperature, and differential oxidation growth of the highly doped areas causes a thick field oxide to grow outside the trenches while only a thin oxide grows over the selected areas.

Abstract: A pressure-wave cycled, repetitively pulsed gas laser comprises a laser cavity having open first and second ends, a channel connecting the first and second sides of laser cavity and a lasing initiation mechanism including two electric discharge electrodes. The electrode discharge generates a shockwave and associated pressure ridge. The channel may be a conicoidical channel of which the first and second open sides of the laser cavity form, respectively, large and small entrances for the shock wave and pressure ridge whereby when the wavefronts meet in the channel the energy thereof cancels in proportion to the entry areas and the resultant wave proceeds to the small entrance where it is accelerated by the nozzle action of the small entrance, entrains non-disassociated gases and circulates the gases through the laser cavity.

Abstract: A combination of logic circuits perform logical operations on data and include a plurality of shift register latches. Each shift register latch includes a latch means for the storing of data, an isolation means for isolating the latch means from data and clock signals connected logic circuits when the isolation means is at a first state, and for conducting data to the latch means when the isolation means is at a second state. Each shift register latch also includes a power reduction means for reducing the power consumed by the isolation means and the latch means.