Abstract: An MOS/LSI type dynamic RAM with single 5 V supply and grounded substrate employs a guard ring surrounding the cell array to prevent pattern sensitivity in testing. The guard ring is an N+ region biased at Vdd over a deep P+ region in a P-substrate, producing a built-in electric field which attracts diffusing minority carriers into a collecting junction. A standard process for making double-level poly memory devices is modified by adding a P+ implant and deep drive-in prior to field oxidation.

Abstract: A redundant column circuit includes a row shared predecoder (12) and predecoders (16), (18) and (20). The predecoders (16-20) are input to a one-of-sixty-four decoder (28) for providing sixty-four decoded outputs therefrom, each of which is input to a one-of-four multiplexer (30). Each of the multiplexers (30) selects one of four normal decode outputs and one of four redundant decode outputs. The selected decode output is determined by the four outputs from the row shared predecoder (12). A switch bank (32) of single pole double throw switches selects between a normal and a redundant output with the redundant output having the address associated therewith incremented by one. The output of the switches in the bank (32) is input to the deactivation circuits (36) for output therefrom to a memory array (38). The memory array (38) has a redundant column (R) in parallel therewith which is controlled by the first switch in a the switch bank (32).

Abstract: A semiconductor dynamic read/write memory device having an array of rows and columns of one-transistor cells employs a single-ended sense amplifier connected to a whole column line, rather than a differential sense amplifier having two inputs connected to column line halves. The single-ended sense amplifier includes an input circuit responsive to a selected threshold voltage, and the output of the amplifier is coupled back to the column line. A dummy cell circuit applies a fixed charge to the column line, so the threshold is exceeded if the selected memory cell stores a 1, but not if a zero is stored.

Abstract: Using a method according to one embodiment of the present invention, an EPROM array may be fabricated providing a dense EPROM array.First the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1 to 1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface.

Abstract: A method and apparatus for testing VLSI processors using a bit-sliced bus-oriented data path include data and control monitors and BIT for the on-chip memory. The data monitor is used to compress output data produced by the data path. BIT implementation of a functional test coupled with the data monitor are used for an off-line self-test of the data path in field. The control monitor is used to decouple the testing task of the control section from that of the data path.

Abstract: The disclosure relates to a semiconductor substrate having an active area for formation of an IMPATT device which is formed as a plurality of separated fingers having a common n+ region to spread the area over which the IMPATT is disposed and which provides such additional area for dissipation of heat through the substrate.

Abstract: The disclosure relates to a monolithic circuit and method of making same which includes the use of two substrates of different semiconductor materials or two substrates of the same semiconductor material wherein the processing steps required for certain parts of the circuit are incompatible with the processing steps required for other parts of the circuit.

Abstract: A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of storage elements to a plurality of data lines. Control circuitry is also provided that is connected to the array for regulating the reading and writing of data to and from the data lines to the storage elements addressed by the address lines. A pipeline circuit is also provided that is connected to the address lines and to array of storage elements to store in response to the control circuit an address contained on the address lines. This memory system architecture allows for the address to be stored to allow the second address to be placed on the address lines while the first addressed data is being accessed from the memory array. This memory system also provides for the parity to be generated for the data in the array during the access of the data for the first address or after the pipeline circuit has been loaded with the second address.

Abstract: A linear spatial light modulator with two offset rows of pixels for slight overlap of images, and a printer system using such a spatial light modulator with dark field projection optics is disclosed. The pixels include electrostatically deflectable elements which all bend in the same direction to permit use of dark field projection. The addressing electrodes for the elements are beneath the reflecting surface and arranged perpendicular to the rows of pixels with half on each side of the rows. The printer uses a xerographic engine for conversion of modulated light into print, and an entire row is printed without any scanning.

Abstract: An electronic thermal printer has a thermal printhead to which is applied a train of pulses which is pulse width modulated. A power switch connects and disconnects the printhead from a DC power source. The pulse train is integrated, scaled and applied as an input to a comparator circuit. The thermal printhead has a temperature sensing diode whose output is applied, as a reference voltage, to the other input of the comparator. During a print cycle, the output of the temperature sensing diode is cut off and the reference voltage is capacitively stored and held as the reference voltage. The output of the comparator circuit clears a latch circuit whose input is provided by a system clock and whose output is connected to control the power switch. The comparator provides an output when the integrated voltage reaches the reference voltage, clearing the latch. Since the latch is supplied with signals from the system clock, a constant frequency is maintained.

Abstract: A test circuit, called a universal testing block (UTB) for on-chip testing of a VLSI subsystem such as a ROM or an ALU has several modes, including test generator and test evaluator, formed on the VLSI chip. The test generator circuit includes means for applying a predetermined test pattern to an input channel of the subsystem and may be a generator for generating pseudorandom test patterns for application to the subsystem. Alternatively, the test generator may be a counter which can be selectively activated to generate a binary up-count. The UTB also has a shift register mode having a serial input and output to enable serial data to be shifted into and out of the subsystem in parallel fashion. The test evaluator circuit receives output signals from the subsystem, and includes a parallel signature analyzer to generate a signature of the subsystem after the application of the test patterns by the input circuit to indicate whether the subsystem is fault-free.

Abstract: A display circuit includes an input circuit to receive data to be displayed that is connected to segment output circuit which further includes a switching architecture that provides a switching signal of greater magnitude than the voltage supplied to the switch in order to provide output signals to a plurality of display segments. The display circuit further includes display timing circuit that provides a second switch which in turn provides a signal of greater magnitude than the magnitude of the voltage supply to the switch in order to provide output signals to the display segments to signify time intervals. The architecture of this display circuit is suitable for interface to liquid crystal display devices. The input interface is suitable for connection to a four bit microcomputer.

Abstract: A molecular beam epitaxy system wherein the wafer on which epitaxial deposition is to occur is not soldered to a substrate holder. Instead, a substrate holder with a lip approximately as high as the thickness of the wafer is used, and a retaining ring attaches to the substrate holder to hold the wafer in place during the growth cycle. The retaining ring, like the substrate holder, is made of high-purity refractory material, such as arccast molybdenum. The substrate holder and retaining ring are dimensioned to hold the wafer somewhat loosely, to allow for thermal expansion during the cycling up to growth temperature, which is typically about 600.degree. C.

Abstract: A MOS read only memory, or ROM, is formed by a process compatible with standard P-channel or N-channel metal or silicon gate manufacturing methods. The ROM is programmed either after the protective nitride layer has been applied and patterned, usually the last step in the slice processing method before electrical testing of the devices, or after the electrical testing of the devices. All potential MOS transistors in the ROM array are initially at a logic "0" or a logic "1". An electron beam slice printing machine is used to program the selected transistors in the ROM array to change their logic state by exposing the gates of the selected transistors to an electron beam. The gates to be exposed are predetermined by a coding on a magnetic tape which corresponds to the desired ROM code. No electron beam mask is necessary since the beam only exposes in selected areas.

Abstract: N-channel devices are fabricated with lightly doped drain/source extensions in a CMOS process, without the requirement of an extra mask level. A merged mask technique uses an oversized version of the N-channel gates, expanded by two alignment tolerances per side, combined with the regular N+ source/drain mask. The oversized gate photoresist prevents the heavy N+ source/drain implant from counterdoping the previously introduced lightly doped drain blanket implant. In the P-channel regions the N-type LDD extensions are counterdoped by the regular P+ source/drain implant. This high-voltage process provides 20 V parts with 4 micron geometries, scalable to other voltages.

Abstract: A housing has a switch chamber in which an electric switch is placed and a recess in which is received a snap acting, thermally responsive disc which actuates and deactuates the switch upon snapping from one configuration to another. A drop in thermal biasing assembly used to modify the operating temperature of the disc has a pair of cylindrical film type resistors electrically connected in parallel circuit relation and physically connected to a pair of connectors. An assembly having resistors of a rating chosen for a particular application is dropped into the recess before the disc is assembled, the connectors sliding into matching bores formed in the housing. The connectors are attached to suitable terminals and the disc is then placed over the thermal biasing assembly to provide a multiple temperature operating thermostat.

Abstract: The disclosure relates to a method for producing single crystal silicon from a polycrystalline silicon melt wherein dopants such as oxygen and nitrogen are uniformly distributed in the crystal both along the crystal axis and radially therefrom. This is accomplished by identifying the correct species in the melt and above the melt and determining the thermochemical equilibrium between the two chemical species which lead to a change of the composition of the silicon single crystal during the entire growth process. This approach effectively circumvents the segregation coefficient during the growth process through the control of the concentration of the dopants in the melt.

Abstract: A circuit for clamping the base of an output pull-down transistor includes a clamp transistor connecting the base of the pull-down transistor to a ground node and a drive circuit for rapidly turning on the clamp transistor in response to a high-to-low transition on an input node. The drive circuit includes a string of Schottky diodes connecting the base of the clamp transistor to the collector of a transistor whose base is responsive to the voltage on the input node.

Abstract: A cylinder pressure transmitter has means mounting piezoelectric means to provide an electrical signal corresponding to the pressure of a cylinder of an internal combustion engine and has electronic means on the mounting means to amplify the signal for transmission to computer control means for regulating engine operation to improve performance. The electronic means are mounted on an insulating substrate which is secured to a rigid support in a housing. Guide means and locating means provided on the housing and on the mounting means cooperate in mounting the housing on the mounting means and contact means on the piezoelectric and electronic means fit together in an improved manner to provide reliable interconnection between the electronic and piezoelectric means and to retain that interconnection even when subjected to engine vibrations.

Abstract: Metal contacts and interconnections for semiconductor integrated circuits are formed by a process using direct-reacted silicide to increase step or sidewall coverage. First a thin layer of titanium or other refractory metal is deposited, extending into a contact hole, then polysilicon is deposited and a preferential etch removes all of the polysilicon except on the vertical sides of steps or apertures. A second thin layer of titanium is deposited, then a heat treatment forms silicide to create conductive sidewalls or a plug. Metal contacts then engage the direct-reacted silicide rather than relying upon step coverage.