Abstract: A hermetically sealed, creep acting pressure switch has a sensor assembly comprising a bulged metallic membrane welded between a port fitting and a support. A switch assembly, attached to the sensor assembly, includes a housing which has a switch chamber in which, in one embodiment, a pair of stationary contacts are mounted. A piston having a force receiving surface at one end is biased into engagement with the membrane with an adjustable calibrated force. An electrically conductive contact bridge is mounted on and is movable with the piston. The switch can be normally open or normally closed depending on which side of the contact bridge the stationary contacts are mounted. In an alternate embodiment a miniature switch is mounted in the switch chamber and is adapted to be actuated by the piston.

Abstract: A ring network is comprised of slave devices (96) (98), (100) and (102) that are interconnected on a ring network. The slave device (96) is interfaced with a test/maintenance controller (120) through a serial transmission line (106). The slave device (96) is interfaced with the slave device (98) through a serial transmission line (108). The slave device (98) is interfaced with the slave device (100) through a line (110) and the slave device (102) is interfaced with the slave device (100) through a line (112) with the slave device (102) being interfaced with the controller (120) through a line (114). A clock is generated by the controller (120) and transmitted to each of the slave devices through a node (1188) to provide an asynchronous clock with respect thereto. Each of the slave devices has an internal synchronizing circuit (130) for synchronizing the internal operation of the devices with respect to the controller (120).

Abstract: The disclosure relates to a photovoltaic solar array which is provided with a matrix having spherical photovoltaic diode particles embedded therein in an ordered array, the P-type region of each particle extending to one matrix surface and the N-type region of each particle extending to an opposed matrix surface. Backside metallization is disposed on the matrix backside surface to interconnect the particles extending thereto and frontside conductors are provided on the opposing matrix surface to interconnect the particles extending thereto. The matrix includes two portions, the first portion being a layer extending to the frontside formed of a clear glass. The second portion of the matrix is, in effect, two layers, one disposed at the P-N junctions of the particles being a lead base glass for junction passivation, this layer being overcoated with a reflective layer to provide additional reflectivity of light entering the matrix onto the particles. This increases the amount of light impinging on the particles.

Abstract: A monolithic low noise amplifier is provided having at least one stage. Said stage including a Field Effect Transistor (FET) and an inductive series feedback element comprising a transmission line having an end connected to the FET source and an end connected to ground. A load matching network is attached to the FET drain to provide simultaneous noise match and power match.

Abstract: A cell design for an MOS random access memory is disclosed. Two levels of polycrystalline silicon are used, one for the bias voltage side of the storage capacitors and another for the gates of the MOS transistors and as the bit select line or to connect the gates to the bit select line. The bit select or X address line may overlie both the first and/or second level poly, so space is saved in the cell layout. A "V-groove" anisotropically etched storage capacitor may include the MOS access transistor in one end, formed by double implant.

Abstract: The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.

Abstract: A high-voltage CMOS process, providing (for 5 micron geometries) both field thresholds and junction breakdowns in excess of 20 volts, wherein only one channel stop implant is used. A double-well process in an epitaxial structure is used. Phosphorus is preferably used as the dopant for the N-tank, and boron is used for the blanket channel stop implant. The boron tends to leach into oxide, and the phosphorus tends to accumulate at the surface, and a high field threshold is achieved over both PMOS and NMOS regions.

Abstract: Formation of a plasma etch mask on a film on a substrate by photodecomposition of a gas at selective portions of the film's surface to deposit etch mask material and form the etch mask is disclosed. The photodecomposition by blanket illumination through a photomask and by direct write with a computer controlled laser are both disclosed. The formation of the etch mask can be immediately followed by the plasma etch without breaking vacuum.

Abstract: A test signal, used to initialize an integrated circuit chip for testing, is multiplexed with a data input line of the chip. The test signal circuitry is inactivated during normal operation of the chip. The test circuitry is activated only when a special input signal, which is a voltage at some midpoint between logic states, is applied to the data input.

Abstract: A quartz arsenic cell having a stabilizing valve used to generate hot arsenic vapor which is flowed into liquid gallium, to provide a melt of liquid gallium arsenide from which a crystal can be pulled. The stabilizing valve prevents negative relative pressure from occurring in the quartz arsenic cell, and thus prevents the molten material from being sucked back up into the quartz arsenic cell.

Abstract: An output buffer in an MOS integrated circuit is adapted to provide high output currents to meet high performance requirements under varying operating conditions and has voltage responsive MOS means limiting output current under certain operating conditions to assure circuit reliability while permitting restriction of circuit buss capacities within desirable limits.

Abstract: A memory decoder wherein a power-up device is interposed between a NOR decoder and ground (VSS), rather than between the decoder and VDD. Preferably the signal to the power-up transistor is itself decoded, so that the power-consuming NOR circuits are inactive over a majority of the chip, even during power-up conditions.

Abstract: A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word lines and the gates of the access transistors are formed by the metal strips. No metal-to-silicon or metal-to-polysilicon contacts are needed. The access transistors are made by etching through polysilicon strips which are the capacitor bias plates. The size of the transistor is not determined by alignment accuracy.

Abstract: A portable carrier (10) for storage and transportation of semiconductor slice cassettes in a clean room environment which shields the semiconductor slices from VLF air in people occupied areas includes a base (12), a pair of spring-mounted cradles (14) mounted on base (12) for supporting the semiconductor slice cassette and a cover (16) for disposal on base (12) to provide a sealed volume. Carrier (10) also includes a latch (20) for removably coupling cover (16) onto base (12). Latch (20) includes a handle (22) at the terminal end thereof to facilitate handling and transporting of carrier (10) when cover (16) is locked in place on base (12). A latch tube (24) is mounted proximate the center of base (12) and cooperates with latch (20) to couple cover (16) onto base (12).

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data; however, the accumulator in the data path may be used as a program address source. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. A separate shift or offset is provided in coupling the output of the accumulator to an internal data bus for use in scaling when storing the accumulator contents in internal data RAM specified by instructions.

Abstract: A CMOS sense amplifier for a dynamic read/write memory employs a latch circuit with cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through P and N channel transistors selectively activated by sense clocks. Differential inputs of the sense amplifier are connected to the bit lines. The N-channel transistors are employed for initial sensing, and then both N-channel and P-channel transistors in sequential order for amplification and restoring the 1-level. This results in better balance, and smaller N and P channel latch transistors may be used, saving area, saving power and increasing speed.

Abstract: A low insertion force connector has conductors blanked and formed from metal strip materials and disposed in openings in an insulating connector body. A receptacle portion of each conductor has a bridge formed to extend around the perimeter of a square and disposed inside a body opening and has integral leaf springs extending from the bridge at the respective sides of the square toward a terminal entry end of the opening so that two pairs of the springs are disposed in facing relation around a common axis for receiving a terminal therebetween. The contact surfaces of one pair of springs is relatively closer to the entry end of the body opening than the contact surfaces of the other pair of springs so that a terminal being inserted moves the pairs of springs separately in establishing said spring forces, thereby requiring lesser terminal insertion forces.

Abstract: A method of manufacture of a semiconductor device such as an MOS dynamic read/write memory cell array uses a doped multilevel oxide layer as a diffusion source to create source/drain regions and diffused interconnects. The process is thereby simplified since an ion implant ordinarily used for this purpose is avoided. The doped oxide subjected to a heat treatment for drive-in and densification, then is reflowed after contact holes are etched.

Abstract: A high reliability low cost connector has flat retainers blanked from an electrically conductive sheet metal and inserted into opening in an electrically insulating body. Each retainer has a post at one end extending from an opening at one side of the body and has a pair of integral wings spaced from each other in a plane at its opposite end disposed in the opening at the opposite side of the body. Spring clips are blanked and formed from an electrically conductive sheet metal spring material and are inserted into the body openings so loop portions of the clips fit between the pairs of retainer wings in each opening and are biased into resilient electrical engagement with the retainer wings. Each clip preferably has two pairs of juxtaposed spring leaves integral with the loop spaced at 90.degree. relative to each other around a common axis to grip a terminal inserted between the spring leaves. The loops are also formed with interruptions in each loop in a common location between two adjacent spring leads.

Abstract: A molecular beam epitaxy system wherein the molybdenum substrate holder and the molybdenum ring which assembles to the substrate holder to hold the wafer are kept in vacuum essentially all the time. Wafers are not pre-mounted to substrate holders, but the wafer mounting step is performed in ultrahigh vacuum after a cassette of wafers has already been loaded and outgassed, under ultrahigh vacuum. Thus, the substrate holder can be outgassed separately at high temperatures, and can remain under high vacuum.