Abstract: A CMOS bistable circuit is employed as an address buffer or latch for a semiconductor memory or the like. The circuit includes a pair of differential gated inputs, one from an address terminal, and the other from a reference voltage. The same clock used to gate the inputs also preconditions the circuit to be in a balanced status, and holds off conduction of any transistor in the circuit. In this manner, a circuit of high speed, low power, and minimum complexity is provided.

Abstract: A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate is grounded over P well areas, and connected to the positive supply over the N wells. One-transistor memory cells are of metal-gate construction with N+ drain regions buried beneath oxide, and other transistors are constructed with silicided, implanted, source/drain regions, self-aligned to the metal gates, employing sidewall oxide spacers to provide lightly-doped drains.

Abstract: A digital processor system including several function modules where each module includes circuitry to perform at least one computational task and the circuitry to transfer information containing that modules respective computational task capability to a global memory upon initialization of each module and further circuitry to interface to the global memory upon initialization together with circuitry to interface to the global memory to determine each modules address. Further included is an information bus connected to the function modules and the to global memory. This system configuration allows for the system to self-configure upon power up intialization.

Abstract: A high speed data processor obtains its speed through the efficient transfer of information over separate data and instruction busses, prefetching of instructions, dual working memory and architectural arrangements designed for maximum information transfer. The architecture of the data processor is such that data from any of several sources may be, either in combination or separately, channelled directly through an Arithmetic Logic Unit (ALU) so as to provide quick manipulation of the data since no extra iterations are needed in this movement. The processor uses two scratch pad or working memory areas. Both scratch pad memories communicate directly with the ALU so as to provide two operands, one from each memory and for the operation of the ALU. Two independent registers are provided which allow the linkage of computer words to obtain longer words thereby and a resulting higher precision. This linkage is accomplished by mapping and carrying the most significant bit over to the next sequentially mapped word.

Abstract: A forward looking infrared (FLIR) energy imaging device has been found to include components which are required by the receiver portion of a long-wavelength rangefinder. For example, the FLIR collecting lens system which focuses energy from a scene onto a sensitive, cooled detector array duplicates the function which must be performed by the laser rangefinder receiver. Thus an integrated laser/FLIR rangefinder comprises a laser transmitter for illuminating a target, and an IR energy optic channel having a FLIR for receiving IR energy and producing a visible image representative thereof, said FLIR including an afocal lens system for collecting and focusing energy from the target and energy from the laser return having a wavelength compatible with the band pass of the IR optics and detector onto a cooled sensitive detector.

Abstract: A low power oscillator circuit including a latch connected to two loops. Each loop includes dynamic inverters and static inverters connected in cascade. The loops are connected to the latch such that the output of the final stage is an input to the latch. An initialization circuit is included on one loop to initiate oscillation. Storage capacitors are included in the loops to provide an oscillator output voltage that is greater than the oscillator power supply voltage.

Abstract: An electrically erasable, programmable memory cell array of the floating gate type is made by a process which allows an erase window for the first level polysilicon floating gate to be positioned beneath a third level poly erase line, while maintaining a small cell size. The erase window is not beneath the second level poly control gate, so degrading of the stored charge by the read mechanism is minimized.

Abstract: A composite, light weight vehicular bumper material is disclosed which has a surface layer of stainless steel, a principal layer of a heat treatable aluminum and an intermediate layer of essentially commercially pure aluminum. The stainless steel provides the desired surface finish and durability; the surface can be flash chromed if desired to provide a suitable bright, specular appearance. The layer of heat treatable aluminum is the principal structural component and provides the high ratio of strength to weight needed for the application. The intermediate layer of pure aluminum serves as a transition zone between the principal and surface layers aiding in the development of the maximum bond strength between those two components. In its application the composite is heat treated to obtain desired mechanical strength characteristics.

Abstract: A PSK modem has a transmitter for converting received digital signals into corresponding PSK output signals and a receiver for receiving PSK signals and converting into corresponding digital signals. The receiver has a dual-integrator voltage controlled oscillator in which, during any given cycle of oscillations, one-half of the circuit is integrating toward the threshold voltage while the other half is idle. When the output of the integrating half reaches the threshold voltage, a control flip-flop toggles and the formerly idle integrator half begins to integrate, allowing the other half to stabilize before the next cycle of oscillation.

Abstract: A synchronous decode circuit for an incremental encoder is disclosed which comprises analog-to-digital converters for converting in phase and quadrature encoder signals to transistor-to-transistor logic (TTL) compatible signals, a latch for receiving current logic level signals and the previous logic level signals for a gray code, a programmable read only memory (PROM) for decoding the logic level signals and generating clock and direction enable signals, and gating logic connected to the PROM for gating clock and direction signals to counters of the system, the counters are connected to a latch under control of the computer to latch the count of movement in preselected directions for the computer. In another embodiment the PROM includes scaling jumper means or error detection means or both for, respectively, adjusting the range of measurement (scale factor) and indicating error in the logic level signals.

Abstract: A MESFET logic gate wherein a logic switch node is both a-c coupled to the output node, preferably by a capacitor network and is also separately DC coupled to it, preferably by a voltage level shifter circuit. The direct capacitative coupling increases the high-frequency cut-off frequency, and reduces the current requirement of the voltage level shifter circuit. The voltage level shifter circuit, even using small width devices, provides low frequency and DC response, so that circuits using the gate of the present invention do not require initialization and refresh cycle. Thus, both high speed and low power are attained.

Abstract: A multiple high electron mobility transistor structure without inverted heterojunctions is disclosed. Multiple normal heterojunctions of doped aluminum gallium arsenide grown on gallium arsenide without alternating inverted heterojunctions of gallium arsenide grown on doped aluminum gallium arsenide is achieved by grading undoped aluminum gallium arsenide from the doped aluminum gallium arsenide to the gallium arsenide to avoid an inverted heterojunction.

Abstract: The present invention teaches a two-and-one-half-level resist process, wherein a first planarizing resist layer is applied, an anti-reflective coating (which need not be a photoresist itself) is applied, and then a top photoresist layer is applied. The top layer is patterned conventionally, at a wavelength which the anti-reflective coating absorbs, and a flood exposure (preferably in deep ultraviolet light) is then used to transfer this pattern to the bottom planarizing resist layer. Good patterning of non-planar surfaces despite topography is thus achieved, and pattern degradation due to spurious reflections (e.g., from an aluminum layer being patterned) is avoided.

Abstract: A stacked CMOS structure is disclosed which uses buried N++ source and drain for the non-self-aligned bulk N-channel driver devices together with an oversized polygate on which a non-self aligned P-channel load device is made from a second layer of poly or recrystallized poly. The non-self aligned pair of stacked devices provides increased density of devices per unit area with a simple process at the cost of increased gate to source and gate to drain parasitic capicitances.

Abstract: A single-pole-double-throw microwave monolithic switch is realized by employing shunt connected field effect transistors interconnected with microstrip transmission lines on a gallium arsenide substrate. A low-pass network, configured with quasi-lumped elements, is used to achieve a 90.degree. phase shift between the transistors and the input point. The FET gate width is selected to yield the appropriate source-drain capacitance, which forms one element of the low-pass network comprising the respective switch output path. Use of this inventive structure yields the bandwidth offered by the conventional shunt switch and the small size achievable in the series switch configuration.

Abstract: An electronic output buffer includes an inverter connected to an input line with several circuit devices for driving an output. The buffer further includes the programmable capability at manufacture for selecting one of several buffer configurations by selectively connecting the inverter and the input line to the circuit driving devices and by selectively connecting the circuit driving devices to one of at least two voltage sources.

Abstract: A connector or socket for detachably mounting an integrated circuit unit on a printed circuit board has single beam contact members precisely located and secured in respective recesses in an electrically insulating body. The contact members are formed of a strip material and each has a spring beam part extending up from a base to loop over the base and a post part extending down from the opposite end of the base. The connector body recesses are open at their bottom end to receive the loop contact portions therein and have a integrally formed stop member projecting into the recesses at their bottom end which permits the beam part of the contact members to pass by during assembly of a contact member into its recess and then serves to limit downward movement of i.c. terminals and isolate the distal end portion of the i.c. terminals from solder material.

Abstract: A snap-acting thermostatic electric switch in which a snap-acting thermostatic disc is physically attached to a heater plate which in turn mounts movable contacts. A stepped rivet loosely mounts the disc and is headed over to tightly mount any one of a series of heater plates having different thicknesses. The heater plate is shaped to allow unimpeded snap motion of the disc yet provide improved heat conduction to the disc. The disc and plate are mounted on a spider support which is adjustably positioned within the switch compartment by means of a combination rivet and screw received in a threaded bore of the base of the switch. An insulator is loosely received on the base and is biased thereagainst by a spring which also biases the spider upwardly to provide positional stability. Another spring is placed between the spider and the heater plate to optimize contact opening.

Abstract: A semiconductor dynamic read/write memory device using one-transistor storage cells and balanced bit lines employs a differential sense amplifier having dual sets of transistors for both the N-channel and P-channel transistor pairs in a CMOS flip-flop circuit. One set of P and N channel transistors is cross-coupled in the conventional manner, and the other set is cross-coupled by way of series transistors which are shut off for write operations, bypassing static loads for write.

Abstract: A control device is shown for a fuel supply system for an automotive engine having a heater which is energized, deenergized and then reenergized in sequence to heat a thermostat metal coil spring over a selected temperature range to regulate opening of a carburetor choke during engine warm up. Contacts are connected between a power source and the heater and a pair of dished bimetal elements having central apertures therein are arranged in facing relation to each other between the contacts, the bimetal elements being adapted to move to inverted dished configuration as they are heated to respective different temperatures within the noted temperature range. The contacts are engaged with each other through the element apertures when engine operation is initiated, are separated when one of the elements moves to its inverted configuration in response to heating of the element, and are then reengaged as the second element moves to its inverted configuration in response to further heating.