Abstract: A motor starting device for de-energizing the starting winding the required motor speed is reached comprising electromagnetic means (3) to urge actuation of the switching means (20,21) and a latch member (10) controlled by a thermal temperature-balanced bimetallic strip (5) to prevent switching until the bimetallic strip (5) reaches a selected temperature through current flow flow therethrough.

Abstract: A silicon accelerometer employing the piezoresistive effect of single crystal silicon to measure the flexure of semiconductor beams supporting a semiconductor mass. In one embodiment a rectangular semiconductor center mass is supported at each corner by a semiconductor beam parallel to one side of the center mass and perpendicular to the adjacent beams, each of the beams having an implanted resistor at the stationary end thereof. The crystal planes and relative orientations of the resistors are selected so that two resistors always increase, and two always decrease their resistance by the same amount as the center mass is displaced, which allows them to be connected in a Wheatstone bridge having a symmetric differential output.

Abstract: A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is selfaligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.

Abstract: An electrically programmable read only memory or EPROM is formed by an MNOS process compatible with N-channel silicon gate manufacturing methods. Row address lines and gates are second level polysilicon, and output and ground lines are defined by elongated N+ regions formed beneath thin field oxide. Each storage cell is an MNOS transistor having an enhancement mode MOS transistor in series with it. The gates of the MNOS transistors are program address lines for programming and are formed by first level polycrystalline silicon. Each MNOS transistor in the array is programmed to be a logic "1" or "0" by proper voltages applied to row, output and program address lines to store charge at the oxide-nitride interface and thus change the threshold voltage for selected transistors. Then readout is provided using the MOS series transistors for access. A very dense array results.

Abstract: A CMOS device configuration in which a complete CMOS inverter is contained in the space normally required for a single NMOS transistor of equivalent geometry. A first polysilicon layer of normal thickness and N+ doping is used for the N channel gate, and a second polysilicon layer is deposited conformally over the oxide which encapsulates the first polysilicon layer. The second polysilicon layer is thin and doped p-type. The second layer is only lightly doped initially, and is then doped more heavily by a low-energy implantation. The portions of the second poly layer which are adjacent to the sidewalls of the gate level in first poly will be shielded from the heavy implantation, and will therefore provide relatively lightly doped p-type channel regions, to form a pair of PMOS polysilicon transistors addressed by the N+ first poly gate electrode. Preferably the channel doping of these polysilicon transistors is at least 10.sup.17.

Abstract: A PMOS input buffer compatible with logic voltage levels provided by NMOS or TTL microprocessor means uses a limited number of transistors of limited size for driving a load in response to such logic and is adapted for use under widely varying operating conditions.

Abstract: The present invention is an electronic learning aid which employs a scanning device for reading printed coded indicia which includes random number modes. A first random number mode provides a flat distribution random number in accordance to a range command. This mode is actuated by scanning coded indicia, firstly, a random number generation command and secondly, a range command. The apparatus then generates a random number from a set of numbers, this set of numbers being determined by the range command. This random number is then employed to select a response which is provided to the user by a speech synthesizer speaking one or more words of human language. In a second embodiment, the random number command enables generation of a random number from among a set in which the probability of selecting one member of the set is different from the probability of selecting other members of the set. This mode could be employed to simulate the number of spots turned upon tossing of two or more dice.

Abstract: A device interface controller provides a sophisticated communication link between a central processor and peripheral digital apparatus. The device interface controller provides simultaneous read and write operations with the peripheral digital apparatus. The device interface controller communicates with the peripheral digital apparatus, providing data to that apparatus and receiving data from that apparatus, as well as commanding the apparatus to perform functions peculiar to the selected device.

Abstract: In order to provide low and exactly repeatable common lead inductance (gate lead inductance) and low feedback parasitics in a common-gate low noise amplifier, a GaAs FET connects the gate electrode to ground at various points along its width by means of an air bridge crossover structure. This structure crosses over the input (source) lines with very low capacitance. Since the gate lead inductance is low in this design, and because in monolithic form this inductance does not vary as is the case for a device grounded using bond wires, common-gate circuit stability is assured. This device preferably uses the well-known pi-gate configuration to provide low drain-gate parasitic capacitance and equal phasing to all parts of the device.

Abstract: An oscillator circuit including a Schmidt trigger that receives an input signal and is connected to a compensating circuit to adjust the trigger points of the Schmidt trigger. The ouput of the Schmidt trigger is connected to a push-pull driver which provides the oscillator output. The oscillator output is fed back through an external resistor and capacitor and input of the Schmidt trigger.

Abstract: Liquid silicon is deposited on a high surface area column of silicon nitride particles, by hydrogen decomposition of trichlorosilane. This is accomplished in an environment heated to a temperature in excess of the melting point of silicon. After deposition, the liquid silicon flows by gravity to a collection point. Preferably a liquid transfer system moves the silicon directly to a crystal pulling operation. The liquid transfer to immediate pulling conserves energy and allows for continual withdrawal of melt from the reactor. The immediate pulling provides additional purification and the crystal thus pulled is preferably used as feedstock for a final crystal pulling operation.

Abstract: A semiconductor dynamic read/write memory circuit using one-transistor storage cells and balanced bit lines with differential sense amplifiers employs dummy capacitors which are the same size as the storage capacitors. The dummy cell produces a signal on the bit line half that of the storage cell due to a level-shift circuitry connected to the dummy cells. The dummy capacitor is precharged to a reference voltage, and at the beginning of an active cycle the dummy capacitor is charge-shared with another capacitance of the same size, to change the reference level. The net signal is thus equal to that of a capacitor one-half the size of the storage capacitors.

Abstract: A method and apparatus for determining the position of a vessel in distress and transmitting an auditory distress message containing the position of the vessel. The apparatus obtains the position of the vessel as determined by a LORAN-C type receiver from either a cassette or directly from the LORAN-C receiver and generates a "Mayday" message including the identification of a vessel, the position of the vessel and the nature of the emergency. The "Mayday" message is synthesized into an auditory human or Morse code message. The language of the auditory message is preferably chosen to correspond with the most likely language used by a possible receiver of the "Mayday" message. Also preferably, the apparatus determines whether the primary distress radio frequency is clear; should the primary distress frequency be in use, the apparatus automatically shifts to a secondary frequency and transmits the "Mayday" message.

Abstract: An electronic circuit interconnection system provides high density mounting of ceramic chip-carrier integrated circuit devices or other beam-lead, dual-in-line (DIP), tape-automated-bonded (TAB), flip-chip, or direct-mounted i.c. devices with wire-bonded interconnects or the like on an economical, dimensionally-stable, interconnection substrate which has high heat dissipating properties. The substrate has glass components which are fused onto etched metal patterns and which are proportioned relative to the metal patterns so that the heat-expansion properties of the substrate correspond to those of the i.c. devices to maintain bond integrity between the i.c. leads and circuit paths on the substrate and so that the substrate has sufficient heat-dissipating properties to permit the high density i.c. mounting.

Abstract: Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.

Abstract: A method of forming a metallic silicide on silicon or polysilicon in which a masking layer such as silicon dioxide is formed on a silicon slice and patterned to expose selected areas of the slice surface. The slice is then sputter etched followed by in situ deposition of a metal layer. The slice is heated to convert the portion of the metal layer in contact with the silicon and/or polysilicon to a metal silicide, then the non-converted metal is removed by a selective etchant. According to another embodiment of the invention a titanium layer is deposited and reacted in an ambient including nitrogen to prevent the out-diffusion of silicon through the TiSi.sub.2 and titanium layers.

Abstract: The specification discloses an automatic shutter timing control for a camera. A voltage supply is applied to a capacitor (38). An electronic switch such as a PMOS gate (44) has conductive and non-conductive states and is connected across the capacitor (38). A pair of transistors (32) and (40) are interconnected in a current mirror configuration and are connected between the voltage supply and the capacitor (38) and are operable in conjunction with a charging resistor (30) such that the capacitor (38) may be charged to a predetermined voltage when the PMOS device (44) is in a non-conductive state. A transistor (54) is operable to receive an electrical control signal in order to sink current from the charging resistor (30) and to prevent current flow through the PMOS device (44). A comparator (42) is responsive to a predetermined voltage on the capacitor (38) to control the camera shutter.

Abstract: A method of removal of photoresist in a manufacturing process for semiconductor devices utilizes burnoff in an oxidizing atmosphere. In order to reduce contamination of underlying silicon dioxide layers, chlorine in the atmosphere getters Na+ ions, etc. The chlorine gas is obtained from HCL added to the oxidizing atmosphere.

Abstract: An electrically programmable read-only memory including a memory array of several bits capable of storing binary data connected to an address circuit for accepting a plurality of bits that designate a selected set of the memory array bits and further connected to a data latch to store data to be programmed in a selected set of memory bits. Further provided is a high voltage circuit for providing a high voltage to the selected set of bits according to the data in the data latch and for programming the data in the selected set of memory array bits. Further provided is an output circuit to provide a precharge signal to the memory array bits and to output data programmed in a selected set of memory array bits designated by the address circuit.

Abstract: In an electronic component manufacturing system, slices are transported in serial fashion between a plurality of work stations. As the slices move through the system, each work station performs a separate manufacturing operation on each slice. The manufacturing operations are performed in immediate succession and within the same time interval so that the slices are processed rapidly and so that slices do not accumulate between the work stations. The slices are maintained in sequence through the system so that the operation of the system is more easily controlled.