Patents Assigned to Texas Instruments
-
Patent number: 4536886Abstract: Pole encoding of a linear predictive all-pole model of speech is accomplished by first finding poles up to the number required for good prediction (e.g., ten). These poles are extracted from the LPC predictor polynomial, using, e.g., a slightly modified Bairstow method. Those poles having a sufficiently narrow bandwidth (i.e., those sufficiently near the unit circle) are separately encoded, since these poles generally correspond to perceptually important formants. The remaining poles are lumped together to form a residual polynomial. The residual polynomial is then transformed to produce reflection coefficients, and all reflection coefficients above the first two are discarded. This provides an efficient spectral-shaping polynomial of a reduced degree. Thus, pole encoding is made possible using a reduced and adaptively varied bit rate.Type: GrantFiled: May 3, 1982Date of Patent: August 20, 1985Assignee: Texas Instruments IncorporatedInventors: Panos E. Papamichalis, George R. Doddington
-
Patent number: 4536835Abstract: A direct AC to AC supply converter in which the control of the bidirectional switches connecting each conductor of a polyphase input supply to each conductor of an output supply is effected by a data processor, the operation of the program of which is synchronized by interrupt with the input supply. The data processor calculates for each output phase 2 values representing pulse widths out of a repeating sequence of 3 (for three phase input and output supplies) and pulse generators produce 3 abutting width modulated pulses in a constant period much shorter than the periods of the supplies. The interrupt operates a software phase locked loop. The pulse generators include an interlock circuit ensuring that the width modulated pulses do not overlap and an overload detector responsive to the turn-on times of the switches. A default logic circuit responsive to hardward or software failure makes the width modulated pulses of equal duration.Type: GrantFiled: January 7, 1983Date of Patent: August 20, 1985Assignee: Texas Instruments IncorporatedInventor: Peter J. Andrews
-
Patent number: 4536817Abstract: An electrical lighting fixture adapted for recessed mounting has structure for mounting and energizing a lamp and has an insulation detecting protector device adapted to interrupt operation of the lamp to prevent overheating of the fixture if thermal insulation is disposed around the fixture in such a way as to excessively block heat dissipation from the fixture. The protector device has structure for mounting the device on the fixture to be subject to representative fixture conditions, has a thermally responsive switch which is actuatable in response to heating to a selected temperature for interrupting operation of the lamp, and has an electrical resistance heater which is thermally coupled to the switch for actuating the switch if thermal insulation excessively blocks dissipation of heat from the protector device.Type: GrantFiled: March 10, 1983Date of Patent: August 20, 1985Assignee: Texas Instruments IncorporatedInventor: Radi Pejouhy
-
Patent number: 4536862Abstract: A seismic cable assembly having an acoustically transparent tubular enclosure has at least one hydrophone electrically connected and positioned within the cable assembly enclosure. The hydrophone is made up of a pair of formed, electrically conductive plates that fit against an insulating seal which also forms a fluid seal, providing a sealed chamber defined by the inside surfaces of the conductive plates. A pair of piezoelectric elements are interconnected and positioned within the sealed chamber, one element mechanically and electrically connected to the inside surface of one of the conductive plates and the other piezoelectric element mechanically and electrically connected to the inside surface of the other conductive plate. When pressure is applied to the conductive plates, they deform, causing the piezoelectric elements to flex. When the elements flex, an electrical output is presented on the conductive plates which serve as terminals.Type: GrantFiled: May 24, 1982Date of Patent: August 20, 1985Assignee: Texas Instruments IncorporatedInventors: Lawrence B. Sullivan, Charng-Wen M. Lo
-
Patent number: 4536664Abstract: A high speed, noninverting circuit for providing an interface between transistor-transistor logic gates and Schottky transistor logic gates. In one embodiment the output of a TTL circuit is coupled through a Schottky diode to an emitter-follower whose input is Schottky clamped. The output of the emitter-follower is coupled to a constant current sink and to the cathode of a low barrier Schottky diode, the anode of which forms the STL-compatible output of the interface circuit. The present circuit thus performs a noninverting level translation with minimum propagation delay.Type: GrantFiled: February 16, 1983Date of Patent: August 20, 1985Assignee: Texas Instruments IncorporatedInventor: Robert C. Martin
-
Patent number: 4535300Abstract: An extended range sample and hold circuit for use in systems such as floating point amplifiers is disclosed. An input differential amplifier receives a varying analog signal which is passed by a transistor sample switch during a predetermined sample period to an integrating differential amplifier having a sample capacitor across its output and inverting input. The charge on the sample capacitor follows the input analog signal. The output of the integrating differential amplifier is connected to a nonlinear circuit which in turn is connected to the noninverting input of an output differential amplifier. The nonlinear circuit provides a resistive path for small signals so that a fraction of the voltage across the sample capacitor is presented at the input to the output differential amplifier. As the signal becomes larger, a nonlinear portion of the circuit provides a signal at the input to the output differential amplifier that approaches the charge on the sample capacitor at one extreme.Type: GrantFiled: June 14, 1983Date of Patent: August 13, 1985Assignee: Texas Instruments IncorporatedInventor: George L. Streckmann
-
Patent number: 4535424Abstract: A memory circuit including several semiconductor substrates, each containing addressable memory elements, address receiving circuitry for receiving address signals and for providing data from the memory in response to the address signals, control circuitry for receiving control signals and for controlling the reading and writing of the memory elements, and interconnection circuitry including elevated portions of the semiconductor substrate connected to contact paths of the semiconductor substrate located above to provide electrical continuity between the addressable circuits of each semiconductor substrate and electrical continuity between the control circuits of each semiconductor substrate.Type: GrantFiled: June 3, 1982Date of Patent: August 13, 1985Assignee: Texas Instruments IncorporatedInventor: Lee R. Reid
-
Patent number: 4535401Abstract: An apparatus having a two wire system for providing both power and data communication between a master controller and at least one subcontroller. The master controller can also be connected through the conductors to submaster controllers which in turn have subcontrollers connected thereto. The master controller is capable of addressing each of the submaster controllers and subcontrollers individually. A three voltage level system can be utilized to provide both power and addressing through the two conductors. Data transmitted by the subcontrollers can be analog and/or digital. A data entry device and an information display device can be connected to the master controller in the same manner as other subcontrollers.Type: GrantFiled: June 30, 1982Date of Patent: August 13, 1985Assignee: Texas Instruments IncorporatedInventor: Thomas C. Penn
-
Patent number: 4535465Abstract: A digital clock generator circuit including a series of inverters connected in cascade with the output of the final stage connected to the input of the first stage in a ring counter fashion. Each inverter includes a first circuit to precharge a node, a second circuit to discharge a node upon occurrence of a selected input signal and a third circuit connected to isolate the node from the circuitry output during the precharge interval. The output of the counter is the output of the final stage. The inverter circuits allow for a low power digital counter by allowing a P-MOS or N-MOS fabrication of devices that do not require continuous power.Type: GrantFiled: December 24, 1981Date of Patent: August 13, 1985Assignee: Texas Instruments IncorporatedInventor: Jerald G. Leach
-
Patent number: 4535299Abstract: A compound floating point amplifier for amplifying an analog signal for presentation to an analog-to-digital converter has two amplifying sections to achieve a wide dynamic range. A signal representative of the rate of change (slew) is derived from a differentiating circuit. The analog signal and the slew rate signal are combined and if both are below a predetermined threshold level, a single step amplification is made in a dual gain amplifier. If both signals are not below the threshold, then there is unity gain through the dual gain amplifier. A sample and hold circuit receives the output of the dual gain amplifier and stores it. Subsequently, the stored voltage is impressed on a binary ladder attenuator which provides a digital word output indicating the required amplification. The voltage stored in the sample and hold circuit is also impressed on a binary gain amplifier system and amplified in accordance with the digital word from the binary ladder attenuator.Type: GrantFiled: June 14, 1983Date of Patent: August 13, 1985Assignee: Texas Instruments IncorporatedInventors: George L. Streckmann, Ralph A. Harris
-
Patent number: 4533888Abstract: A remotely controlled circuit control device has first and second load contact assemblies movable into circuit engagement and circuit disengagement positions relative to one another in which one load contact assembly is operatively connected to a solenoid so that alternate forward strokes of the solenoid moves the one load contact assembly between reset and tripped positions through a push-push mechanism having an indexing portion and a latching portion. An overload mechanism cooperates with the latch portion to cause the load contact assemblies to move to the circuit disengaged position upon occurrence of a fault condition. The second load contact assembly includes pivotably mounted contact members which are linked to the first load contact assembly in such a way that circuit engagement during solenoid energization is precluded.Type: GrantFiled: August 7, 1984Date of Patent: August 6, 1985Assignee: Texas Instruments IncorporatedInventors: Aime J. Grenier, Lyle E. McBride
-
Patent number: 4533843Abstract: A random access read/write MOS memory device consisting of an array of rows and columns of one-transistor memory cells employs a bistable sense amplifier circuit at the center of each column. The sense amplifier is of the dynamic type in that coupling transistors connect the column line halves to the cross-coupled driver transistors. The sources of the driver transistors are connected to ground through a sequentially timed, three step grounding arrangement employing two transistors, one having a dual channel implanted to provide two different threshold voltages. Active load devices connected to the column line halves provide pull-up of the voltage on the one-going column line half to a full Vdd level.Type: GrantFiled: October 15, 1984Date of Patent: August 6, 1985Assignee: Texas Instruments IncorporatedInventors: Joseph C. McAlexander, III, Lionel S. White, Jr., G. R. Mohan Rao
-
Patent number: 4533992Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.Type: GrantFiled: February 22, 1982Date of Patent: August 6, 1985Assignee: Texas Instruments IncorporatedInventors: Surendar S. Magar, Edward R. Caudel
-
Patent number: 4533214Abstract: A light modulating device such as a liquid crystal display or polarizer is fabricated using optically biaxial plastic material as a substrate. The plastic biaxial material replaces the glass substrate of the LCD, or the cellulose acetate butyrate (CAB) of the polarizer. The biaxial material is a type of stretched plastic, which is more flexible than glass, and much thinner in typical display applications. Typical plastic biaxial materials are chemically stable with liquid crystals and much more stable than isotropic plastics (CAB). The material is optically anistropic, but optical axes of the material are chosen to be outside the field of view over which the device will be observed.Type: GrantFiled: September 12, 1983Date of Patent: August 6, 1985Assignee: Texas Instruments IncorporatedInventors: Perry A. Penz, Robert J. Petcavich, William P. Stearns, Larry W. Sanders
-
Patent number: 4532587Abstract: A digital processing system includes an external memory for the storage of program instructions for use with a separate processor that internally contains a memory for temporary storage, an arithmetic and logic means, a register set, control and timing circuitry, and two sets of data paths. The first set of data paths provide access to the external memory for transfer of instructions from the external memory to the processing unit. The second set of data paths provide for the internal routing of instructions data and addresses within the processor unit itself. The data structure for the first set of data paths is different than that for the second set of data paths, providing for an external data structure that is different than the internal data structure of the processor.Type: GrantFiled: August 26, 1981Date of Patent: July 30, 1985Assignee: Texas Instruments IncorporatedInventors: Derek Roskell, John V. Schabowski, Karl M. Guttag, Kevin C. McDonough, Brian Shore, Thomas Preston
-
Patent number: 4531097Abstract: A high frequency amplifier comprising a pair of input transistors forming a differential amplifier stage, with an impedance connected between the common terminals of the input transistors to vary the amplification factor of the amplifier stage. The variable impedance is formed by a diode bridge the a.c. terminals of which are connected to the common terminals of the input transistors and the d.c. terminals of which are connected to a circuit arrangement including current mirrors to feed a d.c. current to the diode bridge to control its impedance and hence the amplification factor of the differential amplifier stage.Type: GrantFiled: June 21, 1983Date of Patent: July 23, 1985Assignee: Texas Instruments Deutschland GmbHInventors: Laszlo Gotz, Hermann Kowatsch
-
Patent number: 4530047Abstract: An electronic digital dual processor system including an interface to an external memory in addition to an internal memory. The dual processor architecture includes dual independent and simultaneously operable registers for the temporary storage of data from an arithmetic and logic unit and for memory addressing. The internal memory includes a ROM for storing instructions and a RAM for storing data. The internal memory is also used to store instructions. Control and timing circuitry is included for the generation of microinstructions for the instructions stored in the memory. The control and timing circuitry provide for the simultaneous and independent execution of the microinstructions involving the dual register sets.Type: GrantFiled: July 20, 1983Date of Patent: July 16, 1985Assignee: Texas Instruments IncorporatedInventors: Gerald D. Rogers, Peter L. Koeppen, Sammy K. Brown, Duane Solimeno
-
Patent number: 4528666Abstract: A memory apparatus including an array of storage elements connected to several addressing lines for selectively connecting a group of the storage elements to multiple data lines. The memory apparatus further includes a parity circuit connected to the data lines and storage elements for selectively generating parity to designate the validity of the selected group of data connected in the portion of storage elements selected by the address lines and storing the parity in the array with the data. Control circuitry is further included for controlling the generation of parity by the parity circuit. The parity generation in this memory system is programmable according to control lines that are connected to the control circuit. The parity circuit may generate the parity output either in the same cycle as the memory access or in the next succeeding cycle of memory access. The output buffer for the parity signal may also be programmable in either a push-pull or a pull-down only configuration.Type: GrantFiled: January 3, 1983Date of Patent: July 9, 1985Assignee: Texas Instruments IncorporatedInventors: James H. Cline, David M. Chastain
-
Patent number: 4528625Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows the alternative of off-chip program fetch in each instruction cycle, with the opcode returned by an external data bus. Data I/O instructions for access to peripherals or external data memory use two machine cycles so that the external ROM fetch is not distributed. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.Type: GrantFiled: February 11, 1982Date of Patent: July 9, 1985Assignee: Texas Instruments IncorporatedInventors: Kevin C. McDonough, Surendar S. Magar
-
Patent number: 4528540Abstract: A thermostat comprising a bimetal switch element reacting at selected temperatures which on one of its ends is fastened on a frame and on the other end is provided with an electric contact adapted to engage a fixed contact provided on the frame, said frame comprising two mutually parallel sheet-like metallic contact carriers forming a base unit, through which two parallel ceramic pins are extending for insulating connection of the two contact carriers and on which pins the contact carriers, with a tight fit, are slidable to and fro relative to one another and are maintained permanently mutually parallel during such mounting, each of said contact carriers having an aperture for lateral exposing of nearly the complete bimetal switch element.Type: GrantFiled: May 14, 1984Date of Patent: July 9, 1985Assignee: Texas Instruments IncorporatedInventors: Jan J. Stiekel, Marinus Hagen, Klaas H. Prins, Philips M. Gerson