Abstract: A digital processing device fabricated on a single semiconductor substrate includes an electrically programmable memory, a random access memory, a central processing unit, all connected by an information transfer bus. An external interface is provided connected to the information transfer bus to provide information contained on the bus to external devices. At least one security bit is provided to determine the status of data stored in the nonvolatile memory and portions of the random access memory. An external interface inhibit circuit is connected to the external interface. Address logic is connected to the information transfer bus to determine when information contained in the electrically programmable memory or the random access memory is being accessed. The address logic also determines the security status of information stored in the selected portions of the random access memory and the electrically programmable memory.

Abstract: An improved cryogenic refrigerator having a drive mechanism suitable for use with gap or clearance seals is disclosed. The drive mechanism includes two reciprocating members, e.g. piston and regenerator/displacer, driven by a common rotating drive shaft. The regenerator/displacer portion of the drive shaft includes a roller at one end in engagement with a rod base plate for driving a rod connected to the regenerator/displacer and a spring for returning the regenerator/displacer simultaneously with the withdrawal of the drive shaft. The piston portion of the drive shaft is connected to a first end of a hollow body. The second end of the hollow body which is opposite the first end has the piston rigidly affixed thereto. The hollow body has a portion adjacent the first end supported by a guide whereby the piston is substantially isolated from side force loads during reciprocation.

Abstract: A three terminal power switch utilizing a lateral thyristor switching circuit is disclosed which exhibits very high gain for both turn-on and turn-off. The gate turn-off capability of the lateral thyristor is accomplished utilizing a secondary shunting thyristor to pull current out of the gate in response to the turn-off signal. The output thyristor is designed to maximize its turn-off gain, and the drive thyristor is designed for optimum forward conduction characteristics; the output thyristor carries approximately ten times the current of the drive thyristor, in one embodiment.

Abstract: A four-way integral switch mechanism allows activation of any one of four switches. This mechanism may be used to position a cursor on a display in both the vertical and horizontal directions where there is a need to control four separate switches to properly locate the cursor. The switch mechanism includes two switch toppers, one of which snaps into and pivots within the other along an axis in a first direction. These two switch toppers then snap into a base which provides a second pivot axis for the second topper which is 90 degrees from the first. The base may have guide pin holes for positioning it as well as the two switch toppers. A spring mechanism engages each of the four lower surfaces of the switch toppers. The switch toppers thereby form one integral whole providing control of four switches by sliding a finger in the direction that cursor movement is desired. Each key has only one degree of freedom, that of rotation, which gives the key a firm controlled feel.

Abstract: A data communication system in which a host data processing system is responsive to an automated sequence of data processing request signals from a remote data processing system. The remote data processing system includes a means for generating and storing in a nonvolatile read/write memory a log on signal which initiates the communications and causes the host system to be responsive to the remote system, a plurality of data processing request signals specifying operations to be performed by the host system and a log off signal for terminating the data communications. Special data processing request signals may include a predetermined delay before transmission of the next data processing request signal by the remote system or may require the host system to transmit a predetermined response signal in order to enable continuation of the sequence of data processing request signals from the remote system.

Abstract: The equation operating system is an improved data and command entry format together with a compatible operation system for use with electronic data processing apparatuses, most particularly with scientific calculators which provide an alphanumeric display of entered equations. This invention also includes a unary operation implementation technique, whereby the operand may be entered either before or after the unary operation.

Abstract: A digital data transmission system for transmitting digital data from digital data handling hardware over a transmission line by analog signal representation and for receiving analog signal representation for reception of digital signals by the digital data handling hardware, incorporates an integrated circuit PSK modem. The modem has a transmitter which includes an encoder for encoding digital data into a first format for conversion to corresponding PSK signals and a transmitter modulator, implemented in switched capacitor circuits, for phase modulating a first carrier frequency according to the first format. The modem has a receiver that includes a demodulator, implemented in switched capacitor circuits, for demodulating PSK signals on a second carrier frequency to provide a second format for conversion to corresponding digital signals, and an encoder for encoding the second format into corresponding digital signals.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data; however, the accumulator in the data path may be used as a program address source for table look-up, for example. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances, such as accumulator addressing. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract: A seismic vibrator source having an hydraulic vibrator coupled to vibrate a ground pad is provided with one or more force transducers such as, for example, load cells, strain gauges, or piezoelectric elements for measuring the force applied to the earth. Signals indicative of the pressure force are applied to a controller for the hydraulic vibrator to adjust control signals to prevent decoupling of the ground pad from the earth during ground seismic operations.

Abstract: A dual peak detector circuit containing a first circuit for receiving the input voltage and storing the maximum value of the input voltage and a second circuit for receiving the input voltage and storing the minimum value of the input voltage. Both are connected to third circuit which also receives the input voltage and provides an output when the input voltage transitions from the maximum input value to the minimum input value. When the input voltage transitions from the minimum input value to the maximum output value, the third circuit alters the output to indicate the input voltage change.

Abstract: A two player game apparatus includes the inputs for the first and second player, together with display for each player with a common display for providing the game status connected to a single electronic digital processor. The processor system further includes two central processing units where one central processing unit performs the game algorithm for one player and the second central processing unit performs the game algorithm for the second player. Each individual's central processing unit provides individual player status for its player input. Both central processing units provide data for the common display.

Abstract: A hand-held application module directs the operation of a programmable manipulator controlled by digital computing means. The module identifies points to which the end effector of the programmable manipulator shall move, programs the programmable manipulator to direct the precise operations relative to the points, selectively runs to one or more points to debug the entered program and retrieves statements for display in its alpha-numeric display facility. Program statements and parameters may be deleted from the program, and program statements and parameters may be added to the program. Entry of commands is made through a keyboard and data is displayed on an alpha-numeric display.

Abstract: An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.

Abstract: A data communication system for controlling communications between a host data processing system and a remote data processing system. The host system communicates a plurality of output condition data signals to the remote system for storage therein. The host system then specifies the recall and output of the condition data signals previously stored in the remote system by transmitting corresponding condition name signals. The host system specifies whether condition data signals or condition name signals are to be sent to the remote system. The host system may send a predetermined number of condition data signals for storage at fixed sequential addresses within the remote system or the host system may specify particular addresses for storage of particular data signals in a memory within the remote system which has previously stored therein a set of default condition data signals. The remote system may include a means for repeating outputs specified by the host system.

Abstract: An electronic talking learning aid is disclosed. The learning aid includes a speech synthesis circuit which, in the embodiment disclosed, includes a digital lattice filter circuit, a voiced/unvoiced speech excitation circuit, a speech parameter interpolator, an input parameter decoder, a digital-to-analog converter circuit and associated timing circuits. The learing aid is also provided with a controller and at least one memory for storing digitized speech parameters as well as other digital data. This other digital data may represent, for instance, correct answers to questions posed by the talking learning aid. A keyboard or other response insertion device is provided to permit an operator to input his or her answers to the questions posed by the learning aid. In the disclosed embodiment, the talking learning aid asks the operator to input the correct spelling of a spoken word and informs the operator whether or not the response was correct.

Abstract: A bipolar ROM having a polysilicon PN junction diode as the matrix element for each bit of storage, wherein the diode is constructed laterally to the associated word line of the array. The word line and diode are implanted with impurities, then metal is deposited on the exposed surfaces of the polysilicon and the structure undergoes a sintering process. A layer of oxide covers the structure and a metal bit line connection is made to the diode P-type section, while the word line and other section of the diode are N-type. P and N type regions may be interchanged, as the polarity of a bit line or word line is a function of drive and sense circuitry. This combination of structure and method allows the use of polysilicon because of the lower sheet resistance and higher speed. Also, the use of PN junction diodes is possible instead of a design requiring Schottky diodes or transistors as matrix elements.

Abstract: This addressing system, advantageously for smaller scale data processors with relatively narrow data paths, facilitates transferring pluralities of multibit data words, e.g., storing or fetching the contents of a multidigit register in a calculator. A bidirectional bus couples a controller and a plug-in memory. The controller generates address, data, and command signals. A decoder receives command signals and outputs signals to a program counter (PC) alternatively indicating a normal mode, in which the controller accesses a single specified memory address, or a multiple access mode, in which a predetermined number of sequential addresses are accessed starting at a specified address. In response to selective command decoder output, the PC alternatively may store received addresses, output stored count values to the controller or to a memory array, or increment the count value in synchronism with data transfers to/from multiple memory locations.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data; however, the accumulator in the data path may be used as a program address source for table-read and table-write, for example. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances, such as accumulator addressing. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data; however, the accumulator in the data path may be used as a program address source for table look-up for accumulator addressing, for example. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. The on-chip program memory may be disabled and only off-chip memory used for program fetch in a systems emulator mode. A non-maskable interrupt procedure used in the emulator mode generates a vector address for the on-chip ROM in switching between memory expansion and emulator modes, using an overvoltage detector to signal this condition.

Abstract: A temperature compensated, phase tolerant sense amplifier for use in a magnetic bubble memory system in which current is applied to the detector resistors only during a bubble detect operation.