Abstract: A data processing apparatus having preprogrammed functions for calculating interest rate dependent variables employs an interest rate mode designation command to enable operation in a selected one of a set of interest rate modes. In the preferred embodiment actuation of an AEC key advances the interest rate mode in a circularly sequential manner among annual percentage rate (sometimes referred to an annual nominal interest rate), annual effective interest rate and annual continuous interest rate. In the preferred embodiment actuation of a key sequence including a compute key and the AEC key enables conversion of an interest rate specified in a first mode into an interest rate specified in the next sequential mode. The data processing apparatus includes a means for outputting an indication of the current interest rate mode.

Abstract: An electronic apparatus for translation from a host language to a non-host language in which the individual word is evaluated as to its contextual meaning. The sequence of words, typically a sentence, within the host language, which is communicated to the electronic apparatus is translated, through a recognition device into a series of recognized words. These recognized words are further refined through analysis of their contextual meaning within the sequence (sentence) so as to differentiate between words of similar pronunciation and between homonyms. The present invention permits the direct entry, from voice, to a translator to a foreign language or alternatively to control language for use with an electronic or electromechanical apparatus.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. The data RAM uses a pseudo-static cell array with refresh. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract: An electronic learning aid selectively provides synthetic speech to an operator. An electro-optic sensor which reads bar code from the pages of a book selects speech words or phrases to be produced by an electronic speech synthesizer. A mode of operation is provided wherein the operator selects an object of comparison such as a displayed picture, number or the like and then seeks to identify one of a plurality of choices which properly associates with the object of comparison.

Abstract: An apparatus and method for depositing a layer of a surface-compatible material from the gas phase onto a selected surface area of a substrate body using a plasma adjacent the substrate body to create a source gas which is decomposed by a laser or other source of energy on the selected surface area. The plasma-generated source gas may be varied by changing targets within the plasma or the reactant gases, and the laser energy may cause decomposition of the source gas by photolysis or pyrolysis or a combination of both.

Abstract: A method and apparatus for encapsulating a lead frame in a flat metal strip and a semiconductor device attached thereto having a mold receiving the semiconductor device and lead frame into a cavity. The strip has a thoroughfare over a solid surface to adjacent said lead frame. A depression in the mold over a portion of the thoroughfare contains a pellet of plastic. A runner extends from the depression over the thoroughfare to transfer liquid plastic from the depression into the cavity.

Abstract: The disclosure relates to a method for removing the unwanted impurities from an HgCdTe alloy which consists of the steps of depositing a thin film on the order of from about 1 to about 100 microns in thickness of tellurium onto the backside of a mercury cadmium telluride bar to insure the presence of a substantial amount of excess tellurium on the backside of the alloy bar and allow the gettering mechanism to work. A protective film to shield the tellurium film from mercury ambient atmosphere is then optionally placed over the tellurium film. The protective film can be formed of a silicon oxide such as SiO and is preferably in the range of about 1000 angstroms to 10 microns or more in thickness. The bar with the tellurium and protective film thereon is then annealed at a temperature of less than 450.degree. C., preferably about 280.degree. C.

Abstract: An improved electrically erasable semiconductor memory device of the N-channel, MOS, double level poly, programmable, read only memory or EPROM type is provided. The device is an array of cells electrically erased and programmed by dual injection into floating gates which are interposed between the channels and control gates. The electrical erasure or programming of the cells is accomplished by applying selected voltages to the source, drain, control gate and substrate to produce injection of electrons or holes.

Abstract: A fluid flow control for an automotive automatic transmission system is shown in which a flag, attached to a free end of a thermostat element is caused to slide over a control orifice to provide a minimum fluid flow at a high reference temperature of the fluid and above and a maximum fluid flow at a low reference temperature of the fluid and below.

Abstract: Disclosed is a non-volatile memory system which includes a first power means for providing a main power source; a read/write memory means for storing and retrieving data signals so long as power is provided; and second power means for coupling to the first power means and to the read/write memory means, the second power means including auxiliary power means for providing a second power source; the second power means further including controller means for continuously providing power to the read/write memory means from either the first power means or the auxiliary power means. In the preferred embodiment, the first power means is within a housing, said housing having a compartment for the receipt of a plug-in module, and the second power means and read/write memory means are contained within the plug-in module. Additionally, in the preferred embodiment, the memory means and the second power means exclusive of the second power source are comprised of a single integrated circuit.

Abstract: The disclosure relates to a two-step for selective anisotropic etching of polycrystalline silicon having a silicon dioxide base thereunder and an exposed opposing face with contaminants thereon including silicon dioxide without leaving a residue wherein the silicon is initially etched with a non-selective etchant for a distance below all contaminants and then an etchant used is a highly anisotropic selective polycrystalline silicon etchant.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract: In stacked CMOS, a single gate in first level polysilicon is used to address both an n-channel device in the substrate and an overlaid p-channel device. The p-channel polysilicon device has its channel self-aligned to the gate, by the use of a boron-doped oxide at the sidewalls of the gate. This boron-doped oxide provides a dopant source which dopes the second polysilicon layer to provide heavily doped source/drain extension regions which are self-aligned to the gate in first poly. A mask level is still required to pattern the sources and drains, but the self-aligned source/drain extension regions mean that the source/drain mask level can have a reasonable alignment tolerance.

Abstract: A power-down inverter comprising three devices in series between supply voltage VDD and ground. A depletion load transistor connects the power supply rail to a first output node; a natural-threshold-voltage transistor, whose gate is controlled by the power-up signal, connects the first output node to a second output node, and an enhancement mode transistor, whose gate is controlled by the input signal to the inverter, connects the second output node to ground. This circuit provides an output (at the first output node) which is never floating, and it is therefore not necessary to use complementary signals for the power-up information. Moreover, the provision of two output nodes permits multiple output states to be available during the power-down mode if desired, depending on the full circuit configuration.

Abstract: A method of making an electrically-programmable memory array in which the memory elements are capacitor devices formed in anisotropically etched V-grooves, providing enhanced dielectric breakdown at the apex of the groove. After breakdown, a memory element exhibits a low resistance to a grounded substrate. The method includes forming access transistors in series with the memory elements, and polycrystalline silicon, deposited to form control gates of the access transistors, also forms address lines. Oxide is formed in the V-groove thinner than the gate oxide thickness formed for the access transistor, providing a lower programming voltage. These factors provide a very small, high speed device.

Abstract: A timer device includes a multiple bit storage circuit to store a numerical value as a series of binary bits and evaluation circuitry to simultaneously compare the value stored in the storage circuitry with a predetermined value. This invention further includes a counter circuit consisting of a multiple bit storage circuit to store an initial counter value, a counter circuit to receive the initial counter value and to decrement the counter in response to a clock signal and an evaluation circuit to produce an output when the counter value is identical to a circuit defined value.

Abstract: A system and method for controlling the tension of an internal diameter saw blade by controlling the temperature of the blade while it is still rotating. The blade temperature is controlled by regulating the temperature of the wash water flow associated therewith. In one embodiment blade tension is periodically measured and, when the tension falls below a predetermined limit, the temperature of the wash water stream is decreased for a period of time until the tension increases to a preselected value.

Abstract: A computing system includes a central processor unit (CPU) in combination with external memory units. The CPU includes an arithmetic logic (ALU), an instruction register, a random access memory, and a control system for interconnecting the functional elements of the CPU via sequential use of a common parallel buss, enabling the CPU to be defined on a single chip. The ALU is capable of performing eight separate arithmetic and logic functions utilizing common logic gates.

Abstract: A liquid crystal display (LCD) capable of automated fabrication facilitated by the use of continuous strips of plastic film on the surface of which corresponding electrode patterns are defined. Liquid crystal material, and spacing means, are sealed between the plastic strips, preferably with the aid of sealing rings formed on one of the film strips; thereby, defining the individual liquid crystal display.

Abstract: A remotely controlled circuit control device has first and second load contact assemblies movable into circuit engagement and circuit disengagement positions relative to one another in which one load contact assembly is operatively connected to a solenoid so that alternate forward strokes of the solenoid moves the one load contact assembly between reset and tripped positions through a push-push mechanism having an indexing portion and a latching portion. An overload mechanism cooperates with the latch portion to cause the load contact assemblies to move to the circuit disengaged position upon occurrence of a fault condition. The second load contact assembly includes pivotably mounted contact members which are linked to the first load contact assembly in such a way that circuit engagement during solenoid energization is precluded.