Abstract: A starting circuit for single phase electric motors including both split-phase and capacitor start motors includes a gate controlled solid state switch serially connected to the start winding of the motor. Rectified reference pulses from a pulse transformer are generated to turn on a first transistor to provide gating current for the solid state switch. Initially, when the motor is energized at zero rpm, the pulses are received at the switch after the start winding current passes through the zero current level to gate the switch to conduct each half cycle and energize the start winding however as the motor speeds up, the pulses are received earlier and earlier relative to the start winding current zero cross over until at a selected speed the pulses are received at the switch prior to the start winding current zero cross over with the result that the switch is no longer gated conductive. When this occurs, the voltage across the switch goes high.

Abstract: An apparatus and method of photolithography with phase conjugate optics having a pump nonlinear medium for producing four way mixing of a beam of coherent electromagnetic radiation incident to said nonlinear medium with a spatically modulated representation of image thereon. The nonlinear medium producing by the phenomenon of four way mixing. A phase conjugated beam having a representation of the image spatically amplitude modulated thereon. The phase conjugated beam is directed toward a surface sensitive to electromagnetic radiation.

Abstract: A video data acquisition system has a video camera for taking pictures of articles and from the picture image digitizes and selects signals within a predetermined amplitude range as representations of pixels of the picture image. A combination of horizontal, vertical and diagonal pixel collection circuitry acquires, in real time, the pixel counts necessary to establish the identity and orientation of the article represented by the image.

Abstract: The equation operating system is an improved data and command entry format together with a compatible operation system for use with electronic data processing apparatuses, most particularly with scientific calculators which provide an alphanumeric display of entered equations. This invention provides an implied multiplication having differing hierarchical ranks when one of a member of a predetermined prefix set entry is followed by one of two differing suffix set entries. Each of these implied multiplications have a differing hierarchical rank than that of explicit multiplication.

Abstract: A carrier having a plurality of leads extending from the lateral sides thereof. The leads extending along the lateral side and over protuberances into depressions in the bottom of the carrier. Each of the depressions is separated by ribs from the other depressions. The ends of the leads disposed in the depressions are prevented from substantial movement by the rib to prevent contact with adjacent leads. At least some of the leads are provided with holes disposed adjacent to the exit of the leads from the enclosure of the carrier. The holes in the leads allow the leads greater flexibility at their portions close to the entrance of the leads into the enclosure. The leads are tapered along their length toward the protuberances. Further, the leads are separated by a width along the lateral side which is within the range of slightly greater than the width of the leads to less than the width of the leads to prevent nesting.

Abstract: A microcomputer device contains a CPU with an arithmetic/logic unit and data/address busses and registers on a single semiconductor integrated circuit having on-chip macrocode and microcode storage. A byte-wide macrocode word is fetched from the ROM and stored in an instruction register in the CPU, then multiple-byte-wide microcode words are fetched from microcode store based on this macrocode word. Also, the microcode can be accessed one byte at a time for processing through the ALU via the data/address busses and registers, as if the microcode was data.

Abstract: A circuit that precharges a node and conditionally discharges the node according to the value of an input. This circuit also includes a device to isolate the node from the output line during precharge. This circuit can be fabricated as a positive channel metal oxide field effect transistor and can be structured to perform the logic function of an inverter or an NAND or NOR gate in simple form. This circuit also includes a capacitor that is connected to the precharge node such that additional charge provided by the clocking circuit is used to add charge to the node such that the charge at the node is greater than the charge provided by the circuit power supply alone.

Abstract: A system for real-time digital processing employs a single-chip microcomputer device having a high-speed on-chip program ROM and a separate data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The on-chip program ROM has a low-level precharge circuit with feedback to improve speed or access time.

Abstract: A processor system employs a self-refresh memory device which comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh address generator circuitry including an address counter or commutator and a multiplexer to insert the refresh address when a command is received or internally generated indicating a refresh cycle. If a refresh command is not being executed, the device is accessed by the processor in the usual manner if a memory address is received.

Abstract: A dynamic read/write memory device constructed in a semiconductor chip of the MOS VLSI type employs an on-chip substrate bias generator which is sequentially clocked by the clocks used in operation of the memory. The impact ionization current associated with each clock operation is thus individually supplied, and when a clock is not used the substrate bias for this clock is not generated.

Abstract: The present invention teaches infrared chalcogenide glass compositions having very low dispersion in the eight to twelve micron range, which are formed as III-V-VI-VII compositions, e.g. 14% (atomic) gallium plus 25% antimony plus 40% selenium plus 21% bromine. The introduction of a group VII component into a chalcogenide glass provides low dispersion, and the group III component compensates for the strong devitrification tendencies of the group VII component and maintains the mechanical properties of the glass.

Abstract: An improved method of making a semiconductor device such as an N-channel, double level poly, MOS read only memory or ROM array is provided; the array is of very dense structure and may be electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon or metal row address lines. The electrical programming of the cells is accomplished by applying selected voltages to the source, drain, control gate and substrate. The very dense array results from a simplified manufacturing process generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride (functioning as an oxidation mask) are created in one mask step before field oxide is grown, then a perpendicular pattern of conductive strips is etched using a second mask step.

Abstract: An electronic digital processing system implemented on a single MOS/LSI semiconductor chip including a ROM for storing instruction codes, a RAM for storing data, an arithmetic logic unit for performing operations on data under control of microinstructions or commands, control circuitry for generating commands in response to the instruction codes in a plurality of central processing units. The fetching of instructions from the ROM, the accessing of data from the RAM, the operation of the arithmetic unit are controlled by the central processing units which share the same data paths that couple the central processing units to the ROM, RAM, arithmetic unit and control circuitry.

Abstract: A programmable device is provided by a thin-oxide avalanche fuse element which is programmed at a voltage below the oxide breakdown level. This device may be used to fix the addresses of faulty rows or columns in a memory having redundant or substitute cells. Upon breakdown, the thin oxide is perforated by small holes which fill with silicon to create short circuits. The source or emitter of the transistor device may be separated from the drain and gate by thick field oxide.

Abstract: A memory cell includes a gated capacitor connected to a first node and also connected to a refresh line. The memory cell further includes a transistor that is also connected to the first node and to a second node with the gate terminal being connected to a second refresh line. The second node is connected to the bit line used to access the bit information contained in the cell. A second transistor is included that has one side connected to a power line, the second side connected to the second node and the gate terminal connected to the first node. A first refresh signal is provided on the refresh line connected to the gated capacitor and a second refresh signal is provided to the gate of the first transistor. The second refresh signal is of a voltage magnitude greater than the voltage provided on the power line and the second refresh signal is also provided at a time during which the first refresh signal is absent.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension. The data RAM has an internal shift arrangement useful in processing convolution algorithms. An addressed location in the RAM is read out and also shifted to the next higher location in one instruction cycle.

Abstract: Semiconductor devices are made by a process in which impurity is introduced, by ion implant, for example, after electrode layers are in place so that inaccuracies in alignment of masks or patterns are compensated. The implanted impurity changes the electrical characteristics of portions of the semiconductor device affected by the registration inaccuracies whereby malfunctions in the completed devices are prevented.

Abstract: In manufacture of VLSI semiconductor devices, the insulator surface upon which a metallization pattern is deposited must be smooth to facilitate lithographic operations. This requires the insulator to be thick and flowed or otherwise treated to eliminate steep edges. A contact hole etched in a thick insulator has steep sidewalls, however, and so chemical vapor deposition is preferrably used for the metallization so the sidewalls will be coated. A thin insulator coating is deposited after the contact holes are etched and prior to metallization to cover the low-resistance flowed insulator and self-align the contacts.

Abstract: The disclosure relates to a plasma etch chemistry which allows a near perfectly anisotropic etch of silicon. A Cl-containing compound such as HCl has HBr added thereto, readily allowing the anisotropic etching of silicon. This is due to the low volatility of SiBr.sub.4. The silicon surface facing the discharge is subjected to ion bombardment, allowing the volatilization (etching) of silicon as a Si-Cl-Br compound. The Br which adsorbs on the sidewalls of the etched silicon passivates them from the etching. This new plasma etch chemistry yields a very smooth etched surface, and the etch rate is relatively insensitive to the electrical conductivity of the silicon.

Abstract: A microcomputer device contains a CPU with an arithmetic/logic unit and data/address registers on a single semiconductor integrated circuit having on-chip macrocode and microcode storage. A macrocode word is fetched from an on-chip ROM and stored in an instruction register in the CPU, then a sequence of microcode words is fetched from the microcode store based on this macrocode word. A check-code based on some function of all microcode bits, or all macrocode and microcode bits, is stored in on-chip ROM upon manufacture. To test a device after fabrication is complete, a test program (resident in ROM or downloaded into on-chip RAM) is executed to access all bytes of microcode (or both microcode and macrocode) and perform some cummulative function on it via the ALU to see if the same check-code is produced. If so, an output indicates a good unit.