Abstract: A method of testing devices under test (DUTs) and testing system are disclosed. The method comprises generating at least one control signal associated with a test pattern structure received from a testing system. The method further comprises selecting M1 number of ports from M number of I/O ports in the DUT to receive scan input corresponding to the test pattern structure based on the control signal, selecting M2 number of ports from the M number of I/O ports to provide scan output based on the control signal, wherein each of M1 and M2 is a number selected from 0 to M, and wherein a sum of M1 and M2 is less than or equal to M. Thereafter, the method comprises performing a scan testing of the DUT based on the scan input provided to the M1 number of ports and receiving the scan output from the M2 number of ports.

Abstract: A method for decoding linear network codes that includes receiving a plurality of packets from an ererror detector and generating a matrix out of the plurality of packets where elements of each column of the matrix correspond to symbols of the plurality of packets. Then decoding across each row of the matrix using only the symbols with highest associated reliability values to obtain a decoded matrix, where each column of the decoded matrix corresponds to a message packet.

Abstract: A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region.

Abstract: A circuit is provided that includes summing circuit for comparing the PWM output signal to the PWM input signal and producing an increment signal if a value of the PWM input signal exceeds a corresponding value of the PWM output signal and producing a decrement signal if a value of the PWM input signal is less than a corresponding value of the PWM output signal. An integrator produces a duty cycle signal by producing an increase in value of the duty cycle signal in response to each increment signal and a decrease in value of the duty cycle signal in response to each decrement signal. A PWM generator produces the PWM output signal in response to the duty cycle signal to cause the duty cycle of the PWM output signal to equal the duty cycle of the PWM input signal with no loss of duty cycle resolution.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: A plastic SON/QFN package (300) for high power has a pair of oblong metal pins (320, 321) exposed from a surface of the plastic (301), the pins straddling a corner (302) of the package; each pin has a long axis (320a, 321a), the long axes of the pair forming a non-orthogonal angle. Package (300) further includes a chip assembly pad (310), acting as a thermal spreader.

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: Apparatus and methods implement aggregation frames and allocation frames. The aggregation frames include a plurality of MSDUs or fragments thereof aggregated or otherwise combined together. An aggregation frame makes more efficient use of the wireless communication resources. The allocation frame defines a plurality of time intervals. The allocation frame specifies a pair of stations that are permitted to communicate with each other during each time interval as well as the antenna configuration to be used for the communication. This permits stations to know ahead of time when they are to communicate, with which other stations and the antenna configuration that should be used. A buffered traffic field can also be added to the frames to specify how much data remains to be transmitted following the current frame. This enables network traffic to be scheduled more effectively.

Abstract: An integrated circuit is provided with a voltage sag detector (VSD) within the integrated circuit package. The VSD is coupled to a voltage reference and to the power distribution bus within the integrated circuit. The VSD has an output for indicating when a voltage level on the power distribution bus sags below a voltage level provided by the voltage reference.

Abstract: Datasheets provide a summary of information about a complex component. A static datasheet provided by a website may be augmented to provide a static design assistance link within the displayed data sheet page. A set of information source links may be provided for display to the user of the website in response to activation of the design assistance link by the user. The plurality of information source links may each contain a link to a different portion of a database in the server containing design information relevant to using the component in a system design. A selected portion of design information may be provided from the database for display to the user in response to activation of one of the plurality of information source links by the user of the website.

Abstract: An apparatus mountable on a wearer's wrist includes a housing having at front portion and an opposite a back portion. The back portion is wearably positionable in contact with the wearer's wrist. The apparatus includes a PPG circuit for generating a PPG signal. The PPG circuit includes a light source and a photosensor on the housing back portion. The PPG signal may be used to continuously determine the wearer's a pulse rate. The PPG signal may also be used in combination with an ECG signal to determine the wearer's instantaneous blood pressure. The ECG signal may also be used to determine the wear's heart rate. The ECG signal may be generated with an electrode mounted on the back of the housing and another electrode mounted on another portion of the housing, such as the back or one or more of the sides.

Abstract: An audio accessory key detection system (40) includes a host circuit (2-3) coupled to communicate via a microphone line (7) with an accessory circuit (3-3) in either a MSFT mode or a digital communication mode. Depletion mode transistors (44-1,2,3) in the accessory circuit are coupled between keys (15-1,2,3) of the accessory circuit, respectively. The depletion mode transistors are allowed to remain conductive for MSFT mode operation. For digital communications mode operation, the host circuit sends a command via the microphone line to a key detector and controller circuit (29A) in the accessory circuit. In response, a voltage is generated to turn the depletion mode transistors off so as to allow digital communications mode operation between the accessory circuit and the host circuit.

Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: One embodiment of the present invention relates to a communications system. The system includes a Highway-Addressable Remote Transducer (HART) transmitter comprising a direct memory access (DMA) module configured to access at least one transmitter lookup table (LUT) using DMA transfers to modulate a HART data packet into a frequency-shift keying (FSK) data signal. The system also includes a HART receiver configured to demodulate a received FSK data signal into a demodulated HART data packet.

Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

Abstract: A method includes receiving a wireless beacon from an ad hoc network at a wireless device, wherein the wireless beacon includes a data structure that encodes at least a portion of a wireless identifier of an access point. The method includes configuring the wireless device from the data structure received from the wireless beacon. The method also includes establishing a wireless network between the access point and the wireless device utilizing at least a portion of the wireless identifier encoded in the data structure.

Abstract: First information is about respective depths of pixel coordinates within an image. Second information is about respective depths of the pixel coordinates within a ground plane. In response to comparing the first information against the second information, respective markings are generated to identify whether any one or more of the pixel coordinates within the image has significant protrusion from the ground plane. In response to a particular depth of a representative pixel coordinate within the image, a window of pixel coordinates is identified that is formed by different pixel coordinates and the representative pixel coordinate. In response to the respective markings, respective probabilities are computed for the pixel coordinates, so that the respective probability for the representative pixel coordinate is computed in response to the respective markings of all pixel coordinates within the window. In response to the respective probabilities, at least one object is detected within the image.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary synchronization signal having first and second segments. The transmitter also includes a secondary scrambling unit configured to provide a scrambled secondary synchronization signal, wherein scrambling agents for the first and second segments are derived from a primary synchronization sequence of the primary synchronization signal. The secondary scrambling unit is further configured to provide an additional scrambling of one of the first and second segments, wherein a second scrambling agent is derived from the remaining segment of a secondary synchronization sequence of the secondary synchronization signal.

Abstract: An optimized floating point multiplier rounding circuit that minimizes the increase of the critical timing path of the calculation. The values of the temporary mantissa required to make the rounding decision are calculated simultaneously by the circuit shown in the invention.