Abstract: A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels, and two body bias elements under the gate, one on each side of the torsion hinge, so that applying a threshold bias between one body bias element and the gate will pivot the gate so that one channel connects the respective source and drain landing pad, and vice versa. An integrated circuit with MEMS logic devices on the dielectric layer, with the source and drain landing pads connected to metal interconnects of the integrated circuit. A process of forming the MEM switch.

Abstract: A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.

Abstract: A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.

Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.

Abstract: In conventional membrane infrared (IR) sensors, little to no attention has been paid toward transmissivity of IR near metal traces. Here, because the substrate of an integrated circuit carrying the sensor is used as a visible light filter, reflection of IR radiation back into the substrate can affect the operation and reliability of the IR sensor. As a result, an arrangement is provided that reduces the area occupied by metal lines by reducing the pitch and compacting the routing so as to reduce the effects from the reflection of IR radiation by metal traces.

Abstract: An apparatus adapts a pre-designed circuit module not supporting a power management protocol to a power management protocol. The apparatus disconnects a bus interface, disables interrupt and stops a clock to the pre-designed circuit module on a external idle request signal.

Abstract: A method is provided. A low dropout regulator (LDO) is disabled during a first mode, and a first reference voltage is selected and applied to a switched-mode converter during the first mode. Also during the first mode, a first output voltage is generated by the switched-mode converter from a power supply, and a first capacitor is overcharged with the first output voltage. The LDO is then enabled during a second mode. During a first portion of a startup period for the second mode, a second capacitor is charged from the first capacitor, and a second reference voltage is selected and applied to the switched-mode converter. Then, during a second portion of the startup period for the second mode, the second capacitor is charged with the switched-mode converter.

Abstract: A debug tool that generates a call stack listing by analyzing the crash memory dump data without relying on register data values. The tool uses information gathered by the compiler and linker when the program was compiled and linked, including the stack's size and location in memory. By examining the stack location in the crash memory dump image in conjunction with the debugging data generated by the compiler and the linker and any existing trace data, the last valid frame may be reconstructed indicating the location of the crash.

Abstract: A method of detecting a signal in radio frequency identification (RFID) transponder (FIG. 1) is disclosed. The method includes receiving a signal (FIG. 7) having a first time in a first logic state (high) and having a second time in a second logic state (low). A weight (700, 702) is determined in response to the first time and the second time. An output signal (from A2D) is produced in response to the weight and one of the first and second logic states.

Abstract: Apparatus and methods implement aggregation frames and allocation frames. The aggregation frames include a plurality of MSDUs or fragments thereof aggregated or otherwise combined together. An aggregation frame makes more efficient use of the wireless communication resources. The allocation frame defines a plurality of time intervals. The allocation frame specifies a pair of stations that are permitted to communicate with each other during each time interval as well as the antenna configuration to be used for the communication. This permits stations to know ahead of time when they are to communicate, with which other stations and the antenna configuration that should be used. A buffered traffic field can also be added to the frames to specify how much data remains to be transmitted following the current frame. This enables network traffic to be scheduled more effectively.

Abstract: An IC processor circuit has an interface for a microphone and a packet switched network. A memory holds bits for converting audible speech from the microphone into digital data in each of successive frames. For each frame the converting includes forming LPC data, LTP lag data, parity check data, adaptive and fixed codebook gain data, and fixed codebook pulse data. The digital data representing the audible speech for the frames is placed into sequential packets, with each packet having a primary stage and a secondary stage. The placing includes arranging data from a first frame of speech in the primary stage of a first packet and arranging data from the first frame of speech in the secondary stage of a second packet, which follows the first packet. The data in the secondary stage includes only LPC data, LTP lag data, parity check data, and adaptive and fixed codebook gain data.

Abstract: Embodiments of the invention provide a DPD system where the transmit reference signal is transformed, including sub-sampling, frequency translation, and the like, to match the feedback signal, which goes thru a similar transformation process, to obtain an error signal. The same transformation is applied to a system model, which may be Jacobian, Hessian, Gradient, or the like, in an adaptation algorithm to minimize error.

Abstract: A computing device uses a recursive discrete Fourier transform (RDFT) engine to reduce time required by a frequency transform module, memory required to hold intermediate products, and/or computing resources used for the testing. In an embodiment the windowing function is integrated and processed simultaneously with the recursive DFT funcions. A frequency-bin power module is configured to determine the frequency bin within the set of frequency bins that has a greatest signal power at various levels of recursion.

Abstract: A transmission gate self-biases its transistors to provide a constant gate biasing that provides a consistent path for an input signal to be cleanly passed to the gate's output and protects the transistors' gate oxide in cases of high input signals. An array of matched transistors are arranged to be biased by a voltage input node and with a current source configured to provide a bias current across individual transistors of the array of matched transistors. A current sink is configured to sink the bias current across the individual transistors to set a bias voltage at a voltage input node to a multiple of a gate-to-source voltage for the individual transistors of the array of matched transistors. A different set of transistors is configured to provide a signal path for an analog input signal.

Abstract: Embodiments of the present disclosure provide a reporting allocation unit, an indicator interpretation unit and methods of operating a reporting allocation unit and an indicator interpretation unit. In one embodiment, the reporting allocation unit includes an indicator configuration module configured to provide reporting interval and offset values of corresponding rank and channel quality indicators for user equipment. The reporting allocation unit also includes a sending module configured to transmit the reporting interval and offset values to the user equipment.

Abstract: According to one embodiment, a method of increasing a perceived resolution of a display includes directing light at a optical dithering element and repeatedly transitioning the optical dithering element from a first position to a second position and then back to the first position such that the mirror alternately reflects light to a first position on the display and then to a second position on the display. Each transition of the mirror includes controlling any overshoot or ringing in the position of the optical dithering element by providing a predetermined drive signal to the optical dithering element to smoothly accelerate and decelerate the element during the traverse between the first and second positions.

Abstract: In accordance with the teachings of the present invention, a system and method for transporting an ancillary data packet in the active area of a video stream are provided. In particular embodiments of the present invention, the method includes coupling a playback server and a digital video projector with a DVI link; placing an ancillary data packet of link encryption metadata in a false line of video in an active area of a frame of video at the playback server, a remainder of the active area comprising true lines of video; transmitting the ancillary data packet from the playback server to a digital video projector through the DVI link; extracting the ancillary data packet from the frame of video at the digital video projector; and displaying the remainder of the active area of the frame of video at the digital video projector.

Abstract: A transmission of information within a wireless cellular network may include a first and second group of samples. A first group of samples is created comprising at least a first and a last subgroup, wherein the last subgroup is same as the first subgroup. A second group of samples created. A transformed set of samples produced by jointly transforming the created first and second group with a discrete Fourier transform (DFT). The transformed set of samples is expanded to produce an expanded set, and the expanded set is transformed with an inverse discrete Fourier transform (IDFT) to produce an OFDM symbol with a fractional payload. The first group of samples is a reference signal (RS), which is known to the receiver before the transmission occurs, while the second group of samples is information data.

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract: An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device.