Patents Assigned to Texas Instruments
  • Publication number: 20140139941
    Abstract: One embodiment includes a preamplifier system. The system includes a reference stage configured to set a magnitude of a clamping voltage for a reference node based on a reference current generated in an adjustable reference current path. The system also includes an output stage comprising an adjustable slew current source that is configured to provide an activation current to the reference node in response to at least one activation signal, the output stage to generate an output current at an output of the output stage with a magnitude that is based on the clamping voltage.
    Type: Application
    Filed: March 15, 2013
    Publication date: May 22, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: JEREMY R. KUEHLWEIN
  • Publication number: 20140143486
    Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.
    Type: Application
    Filed: October 23, 2013
    Publication date: May 22, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Kai Chirca, Matthew D. Pierson
  • Publication number: 20140139297
    Abstract: An apparatus is provided. Transmission line cells are formed in a first region. A first metallization layer is formed over the transmission line cells within a portion of the first region. At least a portion of the first metallization layer is electrically coupled to the plurality of transmission line cells. A second metallization layer is formed over the first metallization layer with an interconnect portion, and overlay portion, and a first balun. The interconnect portion at least partially extends into the first region, and the overlay portion is within the first region. The first balun winding is electrically coupled to the overlay portion and partially extends into a second region. The first region partially surrounds the second region. A third metallization layer is formed over the second metallization layer having a second balun winding within the second region, where the second winding is generally coaxial with the first balun winding.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 22, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Swaminathan Sankaran, Brian P. Ginsburg, Vijay B. Rentala, Srinath M. Ramaswamy, Eunyoung Seok, Baher Haroun, Bradley A. Kramer, Hassan Ali, Nirmal C. Warke
  • Publication number: 20140138805
    Abstract: A system has a leadframe strip and a plurality of integrated circuit dies are each encapsulated in an encapsulant. The encapsulant has a plurality of first cuts and a plurality of second cuts therein. A fixture holds the package in said plurality of first cuts while said plurality of second cuts are made.
    Type: Application
    Filed: September 30, 2013
    Publication date: May 22, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: Donald C. Abbott
  • Patent number: 8729657
    Abstract: A MEMS logic device comprising agate which pivots on a torsion hinge, two conductive channels on the gate, one on each side of the torsion hinge, source and drain landing pads under the channels, and two body bias elements under the gate, one on each side of the torsion hinge, so that applying a threshold bias between one body bias element and the gate will pivot the gate so that one channel connects the respective source and drain landing pad, and vice versa. An integrated circuit with MEMS logic devices on the dielectric layer, with the source and drain landing pads connected to metal interconnects of the integrated circuit. A process of forming the MEM switch.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: James N. Hall, Lance W. Barron, Cuiling Gong
  • Patent number: 8729616
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Imran Mahmood Khan, Allan T. Mitchell, Kaiping Liu
  • Patent number: 8732398
    Abstract: This invention is a data processing system including a central processing unit, an external interface, a level one cache, level two memory including level two unified cache and directly addressable memory. A level two memory controller includes a directly addressable memory read pipeline, a central processing unit write pipeline, an external cacheable pipeline and an external non-cacheable pipeline.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Raguram Damodaran
  • Patent number: 8730075
    Abstract: An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal, wherein if the clock for the charge pump is running faster than an analog front end (“AFE”) video sampling clock, a state-machine control is configured to: skip the charge pump clock period right before a video sample signal falling edge, thereby recovering to a normal operation the next charge-pump clock period, wherein this duty cycle modulation of charge pump clock will not substantially impact charge pump output.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Sualp Aras, Guhaprakash Amudhan, Abidur Rahman, Xiaochun Zhao
  • Patent number: 8727217
    Abstract: A method of detecting a signal in radio frequency identification (RFID) transponder (FIG. 1) is disclosed. The method includes receiving a signal (FIG. 7) having a first time in a first logic state (high) and having a second time in a second logic state (low). A weight (700, 702) is determined in response to the first time and the second time. An output signal (from A2D) is produced in response to the weight and one of the first and second logic states.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ganesh K. Balachandran, Raymond E. Barnett
  • Patent number: 8728846
    Abstract: A thermoelectric device is disclosed which includes metal thermal terminals protruding from a top surface of an IC, connected to vertical thermally conductive conduits made of interconnect elements of the IC. Lateral thermoelectric elements are connected to the vertical conduits at one end and heatsinked to the IC substrate at the other end. The lateral thermoelectric elements are thermally isolated by interconnect dielectric materials on the top side and field oxide on the bottom side. When operated in a generator mode, the metal thermal terminals are connected to a heat source and the IC substrate is connected to a heat sink. Thermal power flows through the vertical conduits to the lateral thermoelectric elements, which generate an electrical potential. The electrical potential may be applied to a component or circuit in the IC. The thermoelectric device may be integrated into an IC without adding fabrication cost or complexity.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Barry Jon Male, Philip L. Hower
  • Patent number: 8732416
    Abstract: A system has memory resources accessible by a central processing unit (CPU). One or more transaction requests are initiated by the CPU for access to one or more of the memory resources. Initiation of transaction requests is ceased for a period of time. The memory resources are monitored to determine when all of the transaction requests initiated by the CPU have been completed. An idle signal accessible by the CPU is provided that is asserted when all of the transaction requests initiated by the CPU have been completed.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Raguram Damodaran, Abhijeet Ashok Chachad, Ramakrishnan Venkatasubramanian, Dheera Balasubramanian, Naveen Bhoria
  • Patent number: 8732370
    Abstract: An arbiter is provided for arbitrating for access to a shared resource by a plurality of requesters and by a background requester in a processing system. A priority value is assigned to each of the plurality of requestors. A multilayer arbitration contest is performed to resolve each conflict in transaction requests to the shared resource, however, a requester of the plurality of requesters having a highest priority value does not always win an arbitration contest. An arbitration contest will be overridden whenever the background requester initiates a transaction request, such that the background requester always wins the overridden arbitration contest. The shared resource is accessed by the winner of each arbitration contest.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kai Chirca, Timothy D Anderson, Amitabh Menon
  • Patent number: 8729877
    Abstract: A method is provided. A low dropout regulator (LDO) is disabled during a first mode, and a first reference voltage is selected and applied to a switched-mode converter during the first mode. Also during the first mode, a first output voltage is generated by the switched-mode converter from a power supply, and a first capacitor is overcharged with the first output voltage. The LDO is then enabled during a second mode. During a first portion of a startup period for the second mode, a second capacitor is charged from the first capacitor, and a second reference voltage is selected and applied to the switched-mode converter. Then, during a second portion of the startup period for the second mode, the second capacitor is charged with the switched-mode converter.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Vadim V. Ivanov, Harish Venkataraman, Daniel A. King
  • Patent number: 8732681
    Abstract: A debug tool that generates a call stack listing by analyzing the crash memory dump data without relying on register data values. The tool uses information gathered by the compiler and linker when the program was compiled and linked, including the stack's size and location in memory. By examining the stack location in the crash memory dump image in conjunction with the debugging data generated by the compiler and the linker and any existing trace data, the last valid frame may be reconstructed indicating the location of the crash.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Darian Robert Peter Sale, Brian Cruickshank
  • Patent number: 8728945
    Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Steven Alan Lytle
  • Patent number: 8731026
    Abstract: A symbol modulation system applicable to a body area network is disclosed herein. The symbol modulation system includes a symbol mapper. The symbol mapper is configured to determine a time within a predetermined symbol transmission interval at which a transmission representative of the symbol will occur. The time is determined based on a value of a symbol and a value of a time-hopping sequence. The time is selected from a plurality of symbol value based time slots, and a plurality of time-hopping sequence sub-time-slots within each symbol value based time slot. The symbol mapper is configured to generate a single guard interval within the symbol transmission interval. The single guard interval is positioned to terminate the symbol transmission interval.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: June Chul Roh, Anuj Batra, Sudipto Chakraborty, Srinath Hosur
  • Patent number: 8732379
    Abstract: An apparatus adapts a pre-designed circuit module not supporting a power management protocol to a power management protocol. The apparatus disconnects a bus interface, disables interrupt and stops a clock to the pre-designed circuit module on a external idle request signal.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Ashutosh Tiwari
  • Patent number: 8732551
    Abstract: A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incoporated
    Inventors: Kai Chirca, Timothy D. Anderson, Amitabh Menon
  • Patent number: 8729473
    Abstract: In conventional membrane infrared (IR) sensors, little to no attention has been paid toward transmissivity of IR near metal traces. Here, because the substrate of an integrated circuit carrying the sensor is used as a visible light filter, reflection of IR radiation back into the substrate can affect the operation and reliability of the IR sensor. As a result, an arrangement is provided that reduces the area occupied by metal lines by reducing the pitch and compacting the routing so as to reduce the effects from the reflection of IR radiation by metal traces.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: May 20, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Walter Meinel, Kalin Lazarov
  • Publication number: 20140135068
    Abstract: An IC processor circuit has an interface for a microphone and a packet switched network. A memory holds bits for converting audible speech from the microphone into digital data in each of successive frames. For each frame the converting includes forming LPC data, LTP lag data, parity check data, adaptive and fixed codebook gain data, and fixed codebook pulse data. The digital data representing the audible speech for the frames is placed into sequential packets, with each packet having a primary stage and a secondary stage. The placing includes arranging data from a first frame of speech in the primary stage of a first packet and arranging data from the first frame of speech in the secondary stage of a second packet, which follows the first packet. The data in the secondary stage includes only LPC data, LTP lag data, parity check data, and adaptive and fixed codebook gain data.
    Type: Application
    Filed: January 21, 2014
    Publication date: May 15, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Krishnasamy Anandakumar, Alan V. McCree