Abstract: A method and apparatus for converting a two dimensional image or video to three dimensional image or video. The method includes segmenting objects in at least one of a two dimensional image and video, performing, in the digital processor, a depth map generation based on low-level features, performing face detection and scene classification on at least one of a two dimensional image and video, and utilizing face detection and scene classification in enhancing the depth map and for converting the at least one of a two dimensional image and video to three dimensional image and video.

Abstract: A method and apparatus for detecting tampering with an image capturing device. The method includes determining a change has occurred in average intensity if an image, determining a percentage area of a foreground mask, detecting related at least one edge and determining at least one edge weight, utilizing the average intensity, the percentage area of the foreground mask, and the at least one edge weight to determining offset of edge blocks of an image, and utilizing the determining offset of edge blocks to detect tampering with an image capturing device.

Abstract: A semiconductor device contains a photodiode which includes a buried collection region formed by a bandgap well to vertically confine photo-generated minority carriers. the bandgap well has the same conductivity as the semiconductor material immediately above and below the bandgap well. A net average doping density in the bandgap well is at least a factor of ten less than net average doping densities immediately above and below the bandgap well. A node of the photodiode, either the anode or the cathode, is connected to the buried collection region to collect the minority carriers, the polarity of the node matches the polarity of the minority carriers. The photodiode node connected to the buried collection region occupies less lateral area than the lateral area of the buried collection region.

Abstract: Integrated circuits and manufacturing methods are presented for creating diffusion resistors (101, 103) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.

Abstract: An imaging device capable of capturing depth information or surface profiles of objects is disclosed herein. The imaging device uses an enclosed flashing unit to project a sequence of structured light patterns onto an object and captures the light patterns reflected from the surfaces of the object by using an image sensor that is enclosed in the imaging device. The imaging device is capable of capturing an image of an object such that the captured image is comprised of one or more color components of a two-dimensional image of the object and a depth component that specifies the depth information of the object.

Abstract: A lead frame strip includes an array of sites arranged in at least one row connected to two exterior side rails which traverse the lead frame strip on two opposite sides. Each of the sites is further connected to the two exterior side rails by subrails which extend between the two exterior side rails. Interior side rails extend between the subrails having a length dimension oriented along a first direction. The interior side rails include at least one punch degating aperture having an aperture length oriented along the first direction, wherein a total of the aperture length along the interior side rails is greater than or equal to the die pad length.

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction.

Abstract: An integrated circuit including a complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) with periodic deep well structures within the memory cell array. The deep well structures are contacted by surface well regions of the same conductivity type (e.g., n-type) in the memory cell array, forming two-dimensional grids of both n-type and p-type semiconductor material in the memory cell array area. Bias conductors may contact the grids to apply the desired well bias voltages, for example in well-tie regions or peripheral circuitry adjacent to the memory cell array.

Abstract: In one aspect of the present invention, an integrated circuit package will be described. The integrated circuit package includes at least two integrated circuits that are attached with a substrate. The integrated circuits and the substrates are at least partially encapsulated in a molding material. There is a groove or air gap that extends partially through the molding material and that is arranged to form a thermal barrier between the integrated circuits.

Abstract: A method to eliminate the delay of multiple overlapping block invalidate operations in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. The cache controller performing the block invalidate operation merges multiple overlapping requests into a parallel stream to eliminate execution delays. Cache operations other that block invalidate, such as block write back or block write back invalidate may also be merged into the execution stream.

Abstract: An apparatus is provided. A polynomial register having a plurality of bits is provided, where the polynomial register is configured to store a user-defined polynomial. A transceiver is coupled to a first bus, a second bus, and the polynomial register. The transceiver includes a self-synchronous scrambler that is configured to generate a scrambled signal from a first signal using the user-defined polynomial and a self-synchronous descrambler that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.

Abstract: A through-substrate via (TSV)-MEMS combination includes a TSV die including a substrate and a plurality of TSVs which extend of a full thickness of the substrate. The TSV die includes a top side surface including circuitry and top side bonding pads thereon, a bottom side surface including bottom side bonding features thereon, and a through-hole through the full thickness of the substrate. A microelectromechanical systems (MEMS) die having a floating sensing structure including solder balls thereon is bound to the top side bonding pads or bottom side bonding features of the TSV die. A layer of adhesive material is surrounding the solder balls, which can provide a sealant ring for the TSV-MEMS bonds.

Abstract: A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 ? of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.

Abstract: A system and method for decoding video encoded using scalable video coding. In one embodiment, a decoder for scalable video coding (SVC) includes an SVC access unit analyzer and decoding logic. The SVC access unit analyzer is configured to examine an SVC access unit prior to layered decoding of the access unit, to determine, based on the examination, what operations the access unit specifies for each layer of the decoding, and to determine, based on the determined operations to be performed for each layer of the decoding, what data to store for use by a subsequent layer of the decoding. The decoding logic is configured to decode the access unit via a plurality of decoding layers; and to store at each decoding layer, for use by a subsequent decoding layer, the data determined by the SVC access unit analyzer to be used by the subsequent decoding layer.

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Abstract: An integrated circuit, in which a minimum gate length of low-noise NMOS transistors is less than twice a minimum gate length of logic NMOS transistors, is formed by: forming gates of the low-noise NMOS transistors concurrently with gates of the logic NMOS transistors, forming a low-noise NMDD implant mask which exposes the low-noise NMOS transistors and covers the logic NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and fluorine into the low-noise NMOS transistors and limiting p-type halo dopants to less than 20 percent of a corresponding logic NMOS halo dose, removing the low-noise NMDD implant mask, forming a logic NMDD implant mask which exposes the logic NMOS transistors and covers the low-noise NMOS transistors and logic PMOS transistors, ion implanting n-type NMDD dopants and p-type halo dopants, but not implanting fluorine, into the logic NMOS transistors, and removing the logic NMDD implant mask.

Abstract: A method for approximate pyramidal search for displacement matching is provided that includes performing a complete window-based search at a coarsest resolution level in a resolution pyramid to determine a best matching point in a destination image for each point in a source image, wherein a displacement from each point to the best matching point is determined, counting, for each displacement of the determined displacements, a number of points having the displacement, selecting displacements from the determined displacements based on the number of points counted for each displacement and a predetermined threshold, and performing a search at the next finer resolution level in the resolution pyramid to determine a best matching point in the destination image for each point in the source image, wherein the search for a best matching point for each point is limited to the selected displacements and a reduced search window around each displacement.

Abstract: An integrated circuit includes two or more communication controllers and a plurality of point to point serial communication lanes for communication external to the integrated circuit. A programmable cross-point circuit allows different sets of serial communication lanes to be coupled at different times to the communication controllers in order to optimize performance of different applications.

Abstract: A process is disclosed of forming metal replacement gates for NMOS and PMOS transistors with oxygen in the PMOS metal gates and metal atom enrichment in the NMOS gates such that the PMOS gates have effective work functions above 4.85 eV and the NMOS gates have effective work functions below 4.25 eV. Metal work function layers in both the NMOS and PMOS gates are oxidized to increase their effective work functions to the desired PMOS range. An oxygen diffusion blocking layer is formed over the PMOS gate and an oxygen getter is formed over the NMOS gates. A getter anneal extracts the oxygen from the NMOS work function layers and adds metal atom enrichment to the NMOS work function layers, reducing their effective work functions to the desired NMOS range. Processes and materials for the metal work function layers, the oxidation process and oxygen gettering are disclosed.

Abstract: An apparatus is provided. The apparatus comprises a polynomial register having a plurality of bits, a first bus, a second bus, and a transceiver that is coupled to the first bus, the second bus, and the polynomial register. The polynomial register is configured to store a user-defined polynomial, and the transceiver includes a pseudorandom bit sequence (PRBS) generator is configured to generate a scrambled signal from the user-defined polynomial and a PRBS checker that is configured to generate a descrambled signal from a second signal using the user-defined polynomial.