Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: A process of generating design rules, OPC rules and optimizing illumination source models for an integrated circuit layout, to form short lines, terminated lines and crossovers between adjacent parallel route tracks, may include the steps of generating a set of template structures which use a set of characteristic design rules, and performing a plurality of source mask optimization (SMO) operations on the set of template structures with different values for the design rules in each SMO operation. In a first embodiment, the SMO operations are run using a predetermined set of values for each of the design rules, spanning a desired range of design rule values. In a second embodiment, the SMO operations are performed in a conditional iterative process in which values of the design rules are adjusted after each iteration based on results of the iteration.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: Circuitry (10-2) for limiting the maximum amount of current (IREF) flowing through a first electrode (DRAIN) of a first transistor (T1) includes an amplifier (14) having an output coupled by a conductor (19) to a control electrode of the first transistor and limiting circuitry (17) including reference current sensing circuitry (22,TSENSE) having a reference current source (IREF—SENSE). A reference current sensing transistor (TSENSE) has a control electrode coupled to the control electrode of the first transistor, a first electrode coupled to a terminal (20) of the reference current source, and a second electrode (SOURCE) coupled to a second electrode of the first transistor. A buffer (T2) has an input coupled to the terminal of the reference current source. The maximum amount is limited in accordance with the reference current source to prevent an increase in magnitude of voltage applied by the amplifier to the first transistor.

Abstract: Communication devices, such as base nodes and modems, that comply with two or more different standards operate on a shared communication channel. To avoid mutual interference, a base node operating under a first standard reserves time using a contention free period designation. The base node allows devices operating under a second standard to communicate during the reserved time by not assigning the contention free period to another device operating under the first standard. Alternatively, a device using the first standard may avoid interference from transmissions generated under the second standard by modifying data packets prior to transmission. A prefix corresponding to a preamble in the second standard is added to the beginning of the data packet created under the first standard. Devices operating under the second standard observe the prefix and recognize that the channel is active. The second-standard devices backoff from transmission thereby minimizing interference.

Abstract: A device includes a sense circuit configured to detect a leakage current from a driver output pad. A current mirror responds to the sense circuit and compensates for the leakage current detected at the driver output pad. A scaled compensation circuit can supply compensation current to the current mirror.

Abstract: A communication receiver including a time domain receive filter to provide a filtered output, the filtered output including colored noise. The receiver also includes a frequency domain, fractionally-spaced equalizer (FSE) unit to receive the filtered output from the receive filter. The FSE unit determines a separate weighting factor for each subcarrier, and the weighting factor is determined based on a noise variance of the subcarrier.

Abstract: A radio frequency (RF) transmitter is provided. The RF transmitter includes first and second drivers that are configured to receive first and second sets of complementary RF signals. Restoration circuits are coupled to the first and second drivers, and a bridge circuit is coupled to the first and second restoration circuits. By having the restoration circuits and the bridge circuit, a common mode impedance and a differential impedance can be provided, where the common mode impedance is lower than the differential impedance.

Abstract: A method of fabricating a MEMS device is disclosed. A metal layer is provided over a first surface of a substrate including over an opening. The metal layer is patterned to define a membrane segment and a pad, with the membrane segment extending at least partially across the opening. An integrated circuit chip is attached over the opening to the membrane segment and pad, with the integrated circuit separated from an extending portion of the membrane segment by a gap. The integrated circuit chip includes a conductive member so that deflection of the extending portion relative to the conductive member can be measured as a change in capacitance.

Abstract: A method and apparatus for predicting reference data transfer scheme for motion estimation. The method includes computing, via the processor, hypothetical rectangle region in reference frame containing all the predicting and reference data for doing motion estimation search around the region, if the macroblock is not the first in a row, utilizing overlap with previously fetched reference data, computing overlap with previously fetched reference data, and transferring needed data, invalidating any predictor, wherein the predictor is not part of the fetched data, and regulating the motion estimation and setting the motion vector to an effective value based on the fetched and computed data.

Abstract: A sputtering target for a conductive oxide, such as SrRuO3, to be used for the sputter deposition of a conductive film that is to be in contact with a ferroelectric material in an integrated circuit. The sputtering target is formed by the sintering of a powder mixture of the conductive oxide with a sintering agent of an oxide of one of the constituents of the ferroelectric material. For the example of lead-zirconium-titanate (PZT) as the ferroelectric material, the sintering agent is one or more of a lead oxide, a zirconium oxide, and a titanium oxide. The resulting sputtering target is of higher density and lower porosity, resulting in an improved sputter deposited film that does not include an atomic species beyond those of the ferroelectric material deposited adjacent to that film.

Abstract: This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect.

Abstract: Systems and methods for building, transmitting, and receiving frame structures in power line communications (PLC) are described. Various techniques described herein provide a preamble design using one or more symbols based on a chirp signal that yields a low peak-to-average power ratio (PAPR). According to some techniques, the preamble may be constructed with one or more different types and/or number of symbols configured to identify a PLC domain operating in close physical proximity to another PLC domain. According to other techniques, one or more preamble symbols may be interspersed within a header portion of a PLC frame to facilitate estimation of a frame boundary and/or sampling frequency offset, for example, in the presence of impulsive noise. According to yet other techniques, a PLC detector may be capable of receiving and decoding two or more types of PLC frames (e.g., using different PLC standards).

Abstract: A method for acoustic echo cancellation in a communication device is provided that includes receiving a first near-end audio signal in the communication device, wherein the first near-end audio signal comprises acoustic echo of a far-end audio signal reproduced by the communication device, and performing echo cancellation on the first near-end audio signal to generate a second near-end audio signal with at least some of the acoustic echo removed, wherein the echo cancellation is performed responsive to presence or absence of double-talk (DT), and wherein a zero-crossing rate (ZCR) is used to detect the presence or absence of DT.

Abstract: In accordance with the teachings of one embodiment of this disclosure, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first outer sidewall surface has a first minimum refractive index. A first anti-reflective layer is formed outwardly from the support structure and outwardly from the substrate. A second anti-reflective layer is formed outwardly from the first anti-reflective layer. The first and second anti-reflective layers each includes respective compounds of at least two elements selected from the group consisting of: silicon; nitrogen; and oxygen.

Abstract: A system is provided for use with a DRAM, a DQS signal provider, a clock signal provider, a DQS line and a clock line. The DQS line can provide the DQS signal from the DQS signal provider to the DRAM. The clock line can provide the clock signal from the clock signal provider to the DRAM. The system includes a clock delay determining portion, a DQS delay determining portion, and adjustment portion and a controlling portion. The clock delay determining portion can determine a clock delay. The DQS delay determining portion can determine a DQS delay. The adjustment portion can generate an adjustment value based on the clock delay and the DQS delay. The controlling portion can instruct the DQS signal provider to adjust a time of providing a second DQS signal based on the adjustment value, wherein the clock delay is less than the DQS delay.

Abstract: A transmitter includes an equalizer for conditioning a data signal in response to a first and a second equalizer setting. The first and second equalizer settings are both associated with a selected point on a two-dimensional search grid. The search grid includes a first equalizer setting and a second equalizer setting for each point on the search grid. The transmitter transmits a data signal across a first channel medium using settings associated with a selected point on the search grid. A receiver analyzes the received signal from the transmitter to determine a signal quality metric. The search grid is used to select settings from neighboring points to produce signals that are evaluated to produce signal quality metrics. The results of the evaluations are used to efficiently search the search grid for optimum equalizer settings for the transmitter.

Abstract: An electronic device includes a bandgap reference voltage generation stage. The bandgap reference voltage generation stage comprises a device with a PN-junction, a current source feeding a first current during a first period of time and a second higher current during a second period of time through the PN-junction. The bandgap reference voltage is generated from a combination of a first voltage drop across the PN-junction during the first period of time and a second voltage drop across the PN-junction during the second period of time. This bandgap reference voltage is formed using switched capacitors.

Abstract: An embodiment of the invention provides a memory on a semiconductor device that has a plurality of memory areas where each memory area has a plurality of consecutive bits. Further, the semiconductor device includes a tag memory having a plurality of trace tags, each trace tag including at least one bit. Each memory area of the memory is mapped to a trace tag that indicates whether the respective memory area is selected for tracing or not. Each memory area and the assigned trace tag are read out and address of the memory area is forwarded to a trace module when an assigned trace tag indicates that the memory area is selected for tracing. When the assigned trace tag indicates that the memory area is not selected for tracing, data and address is discarded.

Abstract: The present invention provides an isolated regulating power converter with opto-coupled feedback of output (Vo) with respect to a reference level (Vset) for regulation to a converter controller. The sense of the feedback signal is such that the opto-coupler LED is ON when Vo<Vset and OFF when Vo>Vset with the effect that the LED current and power loss is zero during the times when Vo>Vset, as is normal case for many controllers at low or no load. This saves power under such circumstances. Additionally, as the LED does not load the output during this time, the proportion of time for which Vo>Vset is increased, meaning that the timing at which the switch must again be on to meet demand is extended, producing a further power saving.